net/mlx: support firmware version query

[dpdk.git] / drivers / net / mlx4 / mlx4.h

diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h
index e0e1b5d..6f41115 100644 (file)
--- a/drivers/net/mlx4/mlx4.h
+++ b/drivers/net/mlx4/mlx4.h
@@ -23,6 +23,9 @@
 #include <rte_ether.h>
 #include <rte_interrupts.h>
 #include <rte_mempool.h>
+#include <rte_rwlock.h>
+
+#include "mlx4_mr.h"
 
 #ifndef IBV_RX_HASH_INNER
 /** This is not necessarily defined by supported RDMA core versions. */
@@ -44,6 +47,9 @@
 /** Interrupt alarm timeout value in microseconds. */
 #define MLX4_INTR_ALARM_TIMEOUT 100000
 
+/* Maximum packet headers size (L2+L3+L4) for TSO. */
+#define MLX4_MAX_TSO_HEADER 192
+
 /** Port parameter. */
 #define MLX4_PMD_PORT_KVARG "port"
 
@@ -66,8 +72,12 @@ struct rxq;
 struct txq;
 struct rte_flow;
 
+LIST_HEAD(mlx4_dev_list, priv);
+LIST_HEAD(mlx4_mr_list, mlx4_mr);
+
 /** Private data structure. */
 struct priv {
+       LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
        struct rte_eth_dev *dev; /**< Ethernet device. */
        struct ibv_context *ctx; /**< Verbs context. */
        struct ibv_device_attr device_attr; /**< Device properties. */
@@ -83,9 +93,19 @@ struct priv {
        uint32_t hw_csum:1; /**< Checksum offload is supported. */
        uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */
        uint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */
+       uint32_t tso:1; /**< Transmit segmentation offload is supported. */
+       uint32_t tso_max_payload_sz; /**< Max supported TSO payload size. */
+       uint32_t hw_rss_max_qps; /**< Max Rx Queues supported by RSS. */
        uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */
        struct rte_intr_handle intr_handle; /**< Port interrupt handle. */
        struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */
+       struct {
+               uint32_t dev_gen; /* Generation number to flush local caches. */
+               rte_rwlock_t rwlock; /* MR Lock. */
+               struct mlx4_mr_btree cache; /* Global MR cache table. */
+               struct mlx4_mr_list mr_list; /* Registered MR list. */
+               struct mlx4_mr_list mr_free_list; /* Freed MR list. */
+       } mr;
        LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */
        LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
        struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];
@@ -111,6 +131,7 @@ int mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
 int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
 int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 void mlx4_stats_reset(struct rte_eth_dev *dev);
+int mlx4_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
 void mlx4_dev_infos_get(struct rte_eth_dev *dev,
                        struct rte_eth_dev_info *info);
 int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete);