* with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5
* device attributes from the glue out parameter.
*
- * @param cdev
- * Pointer to mlx5 device.
- *
- * @param device_attr
- * Pointer to mlx5 device attributes.
+ * @param sh
+ * Pointer to shared device context.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
-mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,
- struct mlx5_dev_attr *device_attr)
+mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)
{
int err;
- struct ibv_context *ctx = cdev->ctx;
- struct ibv_device_attr_ex attr_ex;
+ struct mlx5_common_device *cdev = sh->cdev;
+ struct mlx5_hca_attr *hca_attr = &cdev->config.hca_attr;
+ struct ibv_device_attr_ex attr_ex = { .comp_mask = 0 };
+ struct mlx5dv_context dv_attr = { .comp_mask = 0 };
- memset(device_attr, 0, sizeof(*device_attr));
- err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex);
+ err = mlx5_glue->query_device_ex(cdev->ctx, NULL, &attr_ex);
if (err) {
rte_errno = errno;
return -rte_errno;
}
- device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex;
- device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr;
- device_attr->max_sge = attr_ex.orig_attr.max_sge;
- device_attr->max_cq = attr_ex.orig_attr.max_cq;
- device_attr->max_cqe = attr_ex.orig_attr.max_cqe;
- device_attr->max_mr = attr_ex.orig_attr.max_mr;
- device_attr->max_pd = attr_ex.orig_attr.max_pd;
- device_attr->max_qp = attr_ex.orig_attr.max_qp;
- device_attr->max_srq = attr_ex.orig_attr.max_srq;
- device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr;
- device_attr->raw_packet_caps = attr_ex.raw_packet_caps;
- device_attr->max_rwq_indirection_table_size =
- attr_ex.rss_caps.max_rwq_indirection_table_size;
- device_attr->max_tso = attr_ex.tso_caps.max_tso;
- device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts;
-
- struct mlx5dv_context dv_attr = { .comp_mask = 0 };
#ifdef HAVE_IBV_MLX5_MOD_SWP
dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
#endif
#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
#endif
- err = mlx5_glue->dv_query_device(ctx, &dv_attr);
+ err = mlx5_glue->dv_query_device(cdev->ctx, &dv_attr);
if (err) {
rte_errno = errno;
return -rte_errno;
}
-
- device_attr->flags = dv_attr.flags;
- device_attr->comp_mask = dv_attr.comp_mask;
+ memset(&sh->dev_cap, 0, sizeof(struct mlx5_dev_cap));
+ if (mlx5_dev_is_pci(cdev->dev))
+ sh->dev_cap.vf = mlx5_dev_is_vf_pci(RTE_DEV_TO_PCI(cdev->dev));
+ else
+ sh->dev_cap.sf = 1;
+ sh->dev_cap.max_qp_wr = attr_ex.orig_attr.max_qp_wr;
+ sh->dev_cap.max_sge = attr_ex.orig_attr.max_sge;
+ sh->dev_cap.max_cq = attr_ex.orig_attr.max_cq;
+ sh->dev_cap.max_qp = attr_ex.orig_attr.max_qp;
+#ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
+ sh->dev_cap.dest_tir = 1;
+#endif
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) && defined(HAVE_MLX5DV_DR)
+ DRV_LOG(DEBUG, "DV flow is supported.");
+ sh->dev_cap.dv_flow_en = 1;
+#endif
+#ifdef HAVE_MLX5DV_DR_ESWITCH
+ if (hca_attr->eswitch_manager && sh->dev_cap.dv_flow_en && sh->esw_mode)
+ sh->dev_cap.dv_esw_en = 1;
+#endif
+ /*
+ * Multi-packet send is supported by ConnectX-4 Lx PF as well
+ * as all ConnectX-5 devices.
+ */
+ if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
+ if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
+ DRV_LOG(DEBUG, "Enhanced MPW is supported.");
+ sh->dev_cap.mps = MLX5_MPW_ENHANCED;
+ } else {
+ DRV_LOG(DEBUG, "MPW is supported.");
+ sh->dev_cap.mps = MLX5_MPW;
+ }
+ } else {
+ DRV_LOG(DEBUG, "MPW isn't supported.");
+ sh->dev_cap.mps = MLX5_MPW_DISABLED;
+ }
+#if (RTE_CACHE_LINE_SIZE == 128)
+ if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)
+ sh->dev_cap.cqe_comp = 1;
+ DRV_LOG(DEBUG, "Rx CQE 128B compression is %ssupported.",
+ sh->dev_cap.cqe_comp ? "" : "not ");
+#else
+ sh->dev_cap.cqe_comp = 1;
+#endif
+#ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
+ sh->dev_cap.mpls_en =
+ ((dv_attr.tunnel_offloads_caps &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
+ (dv_attr.tunnel_offloads_caps &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
+ DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported.",
+ sh->dev_cap.mpls_en ? "" : "not ");
+#else
+ DRV_LOG(WARNING,
+ "MPLS over GRE/UDP tunnel offloading disabled due to old OFED/rdma-core version or firmware configuration");
+#endif
+#if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
+ sh->dev_cap.hw_padding = !!attr_ex.rx_pad_end_addr_align;
+#elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
+ sh->dev_cap.hw_padding = !!(attr_ex.device_cap_flags_ex &
+ IBV_DEVICE_PCI_WRITE_END_PADDING);
+#endif
+ sh->dev_cap.hw_csum =
+ !!(attr_ex.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
+ DRV_LOG(DEBUG, "Checksum offloading is %ssupported.",
+ sh->dev_cap.hw_csum ? "" : "not ");
+ sh->dev_cap.hw_vlan_strip = !!(attr_ex.raw_packet_caps &
+ IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
+ DRV_LOG(DEBUG, "VLAN stripping is %ssupported.",
+ (sh->dev_cap.hw_vlan_strip ? "" : "not "));
+ sh->dev_cap.hw_fcs_strip = !!(attr_ex.raw_packet_caps &
+ IBV_RAW_PACKET_CAP_SCATTER_FCS);
+#if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
+ !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
+ DRV_LOG(DEBUG, "Counters are not supported.");
+#endif
+ /*
+ * DPDK doesn't support larger/variable indirection tables.
+ * Once DPDK supports it, take max size from device attr.
+ */
+ sh->dev_cap.ind_table_max_size =
+ RTE_MIN(attr_ex.rss_caps.max_rwq_indirection_table_size,
+ (unsigned int)RTE_ETH_RSS_RETA_SIZE_512);
+ DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u",
+ sh->dev_cap.ind_table_max_size);
+ sh->dev_cap.tso = (attr_ex.tso_caps.max_tso > 0 &&
+ (attr_ex.tso_caps.supported_qpts &
+ (1 << IBV_QPT_RAW_PACKET)));
+ if (sh->dev_cap.tso)
+ sh->dev_cap.tso_max_payload_sz = attr_ex.tso_caps.max_tso;
+ strlcpy(sh->dev_cap.fw_ver, attr_ex.orig_attr.fw_ver,
+ sizeof(sh->dev_cap.fw_ver));
#ifdef HAVE_IBV_MLX5_MOD_SWP
- device_attr->sw_parsing_offloads =
- dv_attr.sw_parsing_caps.sw_parsing_offloads;
+ if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
+ sh->dev_cap.swp = dv_attr.sw_parsing_caps.sw_parsing_offloads &
+ (MLX5_SW_PARSING_CAP |
+ MLX5_SW_PARSING_CSUM_CAP |
+ MLX5_SW_PARSING_TSO_CAP);
+ DRV_LOG(DEBUG, "SWP support: %u", sh->dev_cap.swp);
#endif
#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
- device_attr->min_single_stride_log_num_of_bytes =
- dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes;
- device_attr->max_single_stride_log_num_of_bytes =
- dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes;
- device_attr->min_single_wqe_log_num_of_strides =
- dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides;
- device_attr->max_single_wqe_log_num_of_strides =
- dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides;
- device_attr->stride_supported_qpts =
- dv_attr.striding_rq_caps.supported_qpts;
+ if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
+ struct mlx5dv_striding_rq_caps *strd_rq_caps =
+ &dv_attr.striding_rq_caps;
+
+ sh->dev_cap.mprq.enabled = 1;
+ sh->dev_cap.mprq.log_min_stride_size =
+ strd_rq_caps->min_single_stride_log_num_of_bytes;
+ sh->dev_cap.mprq.log_max_stride_size =
+ strd_rq_caps->max_single_stride_log_num_of_bytes;
+ sh->dev_cap.mprq.log_min_stride_num =
+ strd_rq_caps->min_single_wqe_log_num_of_strides;
+ sh->dev_cap.mprq.log_max_stride_num =
+ strd_rq_caps->max_single_wqe_log_num_of_strides;
+ sh->dev_cap.mprq.log_min_stride_wqe_size =
+ cdev->config.devx ?
+ hca_attr->log_min_stride_wqe_sz :
+ MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
+ DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %u",
+ sh->dev_cap.mprq.log_min_stride_size);
+ DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %u",
+ sh->dev_cap.mprq.log_max_stride_size);
+ DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %u",
+ sh->dev_cap.mprq.log_min_stride_num);
+ DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %u",
+ sh->dev_cap.mprq.log_max_stride_num);
+ DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %u",
+ sh->dev_cap.mprq.log_min_stride_wqe_size);
+ DRV_LOG(DEBUG, "\tsupported_qpts: %d",
+ strd_rq_caps->supported_qpts);
+ DRV_LOG(DEBUG, "Device supports Multi-Packet RQ.");
+ }
#endif
#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
- device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps;
+ if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
+ sh->dev_cap.tunnel_en = dv_attr.tunnel_offloads_caps &
+ (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP |
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
+ }
+ if (sh->dev_cap.tunnel_en) {
+ DRV_LOG(DEBUG, "Tunnel offloading is supported for %s%s%s",
+ sh->dev_cap.tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
+ sh->dev_cap.tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
+ sh->dev_cap.tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : "");
+ } else {
+ DRV_LOG(DEBUG, "Tunnel offloading is not supported.");
+ }
+#else
+ DRV_LOG(WARNING,
+ "Tunnel offloading disabled due to old OFED/rdma-core version");
#endif
- strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver,
- sizeof(device_attr->fw_ver));
-
+ if (!sh->cdev->config.devx)
+ return 0;
+ /* Check capabilities for Packet Pacing. */
+ DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz.",
+ hca_attr->dev_freq_khz);
+ DRV_LOG(DEBUG, "Packet pacing is %ssupported.",
+ hca_attr->qos.packet_pacing ? "" : "not ");
+ DRV_LOG(DEBUG, "Cross channel ops are %ssupported.",
+ hca_attr->cross_channel ? "" : "not ");
+ DRV_LOG(DEBUG, "WQE index ignore is %ssupported.",
+ hca_attr->wqe_index_ignore ? "" : "not ");
+ DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported.",
+ hca_attr->non_wire_sq ? "" : "not ");
+ DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)",
+ hca_attr->log_max_static_sq_wq ? "" : "not ",
+ hca_attr->log_max_static_sq_wq);
+ DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported.",
+ hca_attr->qos.wqe_rate_pp ? "" : "not ");
+ sh->dev_cap.txpp_en = hca_attr->qos.packet_pacing;
+ if (!hca_attr->cross_channel) {
+ DRV_LOG(DEBUG,
+ "Cross channel operations are required for packet pacing.");
+ sh->dev_cap.txpp_en = 0;
+ }
+ if (!hca_attr->wqe_index_ignore) {
+ DRV_LOG(DEBUG,
+ "WQE index ignore feature is required for packet pacing.");
+ sh->dev_cap.txpp_en = 0;
+ }
+ if (!hca_attr->non_wire_sq) {
+ DRV_LOG(DEBUG,
+ "Non-wire SQ feature is required for packet pacing.");
+ sh->dev_cap.txpp_en = 0;
+ }
+ if (!hca_attr->log_max_static_sq_wq) {
+ DRV_LOG(DEBUG,
+ "Static WQE SQ feature is required for packet pacing.");
+ sh->dev_cap.txpp_en = 0;
+ }
+ if (!hca_attr->qos.wqe_rate_pp) {
+ DRV_LOG(DEBUG,
+ "WQE rate mode is required for packet pacing.");
+ sh->dev_cap.txpp_en = 0;
+ }
+#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
+ DRV_LOG(DEBUG,
+ "DevX does not provide UAR offset, can't create queues for packet pacing.");
+ sh->dev_cap.txpp_en = 0;
+#endif
+ /* Check for LRO support. */
+ if (mlx5_devx_obj_ops_en(sh) && hca_attr->lro_cap) {
+ /* TBD check tunnel lro caps. */
+ sh->dev_cap.lro_supported = 1;
+ DRV_LOG(DEBUG, "Device supports LRO.");
+ DRV_LOG(DEBUG,
+ "LRO minimal size of TCP segment required for coalescing is %d bytes.",
+ hca_attr->lro_min_mss_size);
+ }
+ sh->dev_cap.scatter_fcs_w_decap_disable =
+ hca_attr->scatter_fcs_w_decap_disable;
+ sh->dev_cap.rq_delay_drop_en = hca_attr->rq_delay_drop;
+ mlx5_rt_timestamp_config(sh, hca_attr);
return 0;
}
dv_attr.priority = 3;
#ifdef HAVE_MLX5DV_DR_ESWITCH
void *misc2_m;
- if (priv->config.dv_esw_en) {
+ if (priv->sh->config.dv_esw_en) {
/* FDB enabled reg_c_0 */
dv_attr.match_criteria_enable |=
(1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT);
}
sh->tx_domain = domain;
#ifdef HAVE_MLX5DV_DR_ESWITCH
- if (priv->config.dv_esw_en) {
+ if (sh->config.dv_esw_en) {
domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
MLX5DV_DR_DOMAIN_TYPE_FDB);
if (!domain) {
goto error;
}
#endif
- if (!sh->tunnel_hub && priv->config.dv_miss_info)
+ if (!sh->tunnel_hub && sh->config.dv_miss_info)
err = mlx5_alloc_tunnel_hub(sh);
if (err) {
DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err);
goto error;
}
- if (priv->config.reclaim_mode == MLX5_RCM_AGGR) {
+ if (sh->config.reclaim_mode == MLX5_RCM_AGGR) {
mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1);
mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1);
if (sh->fdb_domain)
mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1);
}
sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
- if (!priv->config.allow_duplicate_pattern) {
+ if (!sh->config.allow_duplicate_pattern) {
#ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE
DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?");
#endif
return ret;
}
-/**
- * DV flow counter mode detect and config.
- *
- * @param dev
- * Pointer to rte_eth_dev structure.
- *
- */
-static void
-mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
-{
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_dev_ctx_shared *sh = priv->sh;
- struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
- bool fallback;
-
-#ifndef HAVE_IBV_DEVX_ASYNC
- fallback = true;
-#else
- fallback = false;
- if (!sh->cdev->config.devx || !priv->config.dv_flow_en ||
- !hca_attr->flow_counters_dump ||
- !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
- (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
- fallback = true;
-#endif
- if (fallback)
- DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
- "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
- hca_attr->flow_counters_dump,
- hca_attr->flow_counter_bulk_alloc_bitmap);
- /* Initialize fallback mode only on the port initializes sh. */
- if (sh->refcnt == 1)
- sh->cmng.counter_fallback = fallback;
- else if (fallback != sh->cmng.counter_fallback)
- DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
- "with others:%d.", PORT_ID(priv), fallback);
-#endif
-}
-
/**
* DR flow drop action support detect.
*
#ifdef HAVE_MLX5DV_DR
struct mlx5_priv *priv = dev->data->dev_private;
- if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action)
+ if (!priv->sh->config.dv_flow_en || !priv->sh->dr_drop_action)
return;
/**
* DR supports drop action placeholder when it is supported;
struct rte_eth_dev *eth_dev = NULL;
struct mlx5_priv *priv = NULL;
int err = 0;
- unsigned int hw_padding = 0;
- unsigned int mps;
- unsigned int mpls_en = 0;
- unsigned int swp = 0;
- unsigned int mprq = 0;
struct rte_ether_addr mac;
char name[RTE_ETH_NAME_MAX_LEN];
int own_domain_id = 0;
strerror(rte_errno));
return NULL;
}
- sh = mlx5_alloc_shared_dev_ctx(spawn, config);
+ sh = mlx5_alloc_shared_dev_ctx(spawn);
if (!sh)
return NULL;
- /* Update final values for devargs before check sibling config. */
- if (config->dv_miss_info) {
- if (switch_info->master || switch_info->representor)
- config->dv_xmeta_en = MLX5_XMETA_MODE_META16;
- }
-#if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
- if (config->dv_flow_en) {
- DRV_LOG(WARNING, "DV flow is not supported.");
- config->dv_flow_en = 0;
- }
-#endif
-#ifdef HAVE_MLX5DV_DR_ESWITCH
- if (!(hca_attr->eswitch_manager && config->dv_flow_en &&
- (switch_info->representor || switch_info->master)))
- config->dv_esw_en = 0;
-#else
- config->dv_esw_en = 0;
-#endif
- if (!config->dv_esw_en &&
- config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
- DRV_LOG(WARNING,
- "Metadata mode %u is not supported (no E-Switch).",
- config->dv_xmeta_en);
- config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
- }
- /* Check sibling device configurations. */
- err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev);
- if (err)
- goto error;
-#ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
- config->dest_tir = 1;
-#endif
- /*
- * Multi-packet send is supported by ConnectX-4 Lx PF as well
- * as all ConnectX-5 devices.
- */
- if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
- if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
- DRV_LOG(DEBUG, "enhanced MPW is supported");
- mps = MLX5_MPW_ENHANCED;
- } else {
- DRV_LOG(DEBUG, "MPW is supported");
- mps = MLX5_MPW;
- }
- } else {
- DRV_LOG(DEBUG, "MPW isn't supported");
- mps = MLX5_MPW_DISABLED;
- }
-#ifdef HAVE_IBV_MLX5_MOD_SWP
- if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
- swp = sh->device_attr.sw_parsing_offloads;
- DRV_LOG(DEBUG, "SWP support: %u", swp);
-#endif
- config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
- MLX5_SW_PARSING_TSO_CAP);
-#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
- if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
- DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
- sh->device_attr.min_single_stride_log_num_of_bytes);
- DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
- sh->device_attr.max_single_stride_log_num_of_bytes);
- DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
- sh->device_attr.min_single_wqe_log_num_of_strides);
- DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
- sh->device_attr.max_single_wqe_log_num_of_strides);
- DRV_LOG(DEBUG, "\tsupported_qpts: %d",
- sh->device_attr.stride_supported_qpts);
- DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d",
- config->mprq.log_min_stride_wqe_size);
- DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
- mprq = 1;
- config->mprq.log_min_stride_size =
- sh->device_attr.min_single_stride_log_num_of_bytes;
- config->mprq.log_max_stride_size =
- sh->device_attr.max_single_stride_log_num_of_bytes;
- config->mprq.log_min_stride_num =
- sh->device_attr.min_single_wqe_log_num_of_strides;
- config->mprq.log_max_stride_num =
- sh->device_attr.max_single_wqe_log_num_of_strides;
- }
-#endif
-#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
- if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
- config->tunnel_en = sh->device_attr.tunnel_offloads_caps &
- (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);
- }
- if (config->tunnel_en) {
- DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
- config->tunnel_en &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "",
- config->tunnel_en &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "",
- config->tunnel_en &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : ""
- );
- } else {
- DRV_LOG(DEBUG, "tunnel offloading is not supported");
- }
-#else
- DRV_LOG(WARNING,
- "tunnel offloading disabled due to old OFED/rdma-core version");
-#endif
-#ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
- mpls_en = ((sh->device_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
- (sh->device_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
- DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
- mpls_en ? "" : "not ");
-#else
- DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
- " old OFED/rdma-core version or firmware configuration");
-#endif
- config->mpls_en = mpls_en;
nl_rdma = mlx5_nl_init(NETLINK_RDMA);
/* Check port status. */
if (spawn->phys_port <= UINT8_MAX) {
* register to match on vport index. The engaged part of metadata
* register is defined by mask.
*/
- if (switch_info->representor || switch_info->master) {
+ if (sh->esw_mode) {
err = mlx5_glue->devx_port_query(sh->cdev->ctx,
spawn->phys_port,
&vport_info);
}
if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) {
priv->vport_id = vport_info.vport_id;
- } else if (spawn->pf_bond >= 0 &&
- (switch_info->representor || switch_info->master)) {
+ } else if (spawn->pf_bond >= 0 && sh->esw_mode) {
DRV_LOG(ERR,
"Cannot deduce vport index for port %d on bonding device %s",
spawn->phys_port, spawn->phys_dev_name);
DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n",
priv->dev_port, priv->domain_id);
}
- config->hw_csum = !!(sh->device_attr.device_cap_flags_ex &
- IBV_DEVICE_RAW_IP_CSUM);
- DRV_LOG(DEBUG, "checksum offloading is %ssupported",
- (config->hw_csum ? "" : "not "));
-#if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
- !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
- DRV_LOG(DEBUG, "counters are not supported");
-#endif
- config->ind_table_max_size =
- sh->device_attr.max_rwq_indirection_table_size;
- /*
- * Remove this check once DPDK supports larger/variable
- * indirection tables.
- */
- if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512)
- config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512;
- DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
- config->ind_table_max_size);
- config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
- IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
- DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
- (config->hw_vlan_strip ? "" : "not "));
- config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
- IBV_RAW_PACKET_CAP_SCATTER_FCS);
-#if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
- hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
-#elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
- hw_padding = !!(sh->device_attr.device_cap_flags_ex &
- IBV_DEVICE_PCI_WRITE_END_PADDING);
-#endif
- if (config->hw_padding && !hw_padding) {
+ if (config->hw_padding && !sh->dev_cap.hw_padding) {
DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
config->hw_padding = 0;
} else if (config->hw_padding) {
DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
}
- config->tso = (sh->device_attr.max_tso > 0 &&
- (sh->device_attr.tso_supported_qpts &
- (1 << IBV_QPT_RAW_PACKET)));
- if (config->tso)
- config->tso_max_payload_sz = sh->device_attr.max_tso;
/*
* MPW is disabled by default, while the Enhanced MPW is enabled
* by default.
*/
if (config->mps == MLX5_ARG_UNSET)
- config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
- MLX5_MPW_DISABLED;
+ config->mps = (sh->dev_cap.mps == MLX5_MPW_ENHANCED) ?
+ MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED;
else
- config->mps = config->mps ? mps : MLX5_MPW_DISABLED;
+ config->mps = config->mps ? sh->dev_cap.mps : MLX5_MPW_DISABLED;
DRV_LOG(INFO, "%sMPS is %s",
config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
config->mps == MLX5_MPW ? "legacy " : "",
config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
if (sh->cdev->config.devx) {
sh->steering_format_version = hca_attr->steering_format_version;
- /* Check for LRO support. */
- if (config->dest_tir && hca_attr->lro_cap &&
- config->dv_flow_en) {
- /* TBD check tunnel lro caps. */
- config->lro.supported = hca_attr->lro_cap;
- DRV_LOG(DEBUG, "Device supports LRO");
+ /* LRO is supported only when DV flow enabled. */
+ if (sh->dev_cap.lro_supported && sh->config.dv_flow_en)
+ sh->dev_cap.lro_supported = 0;
+ if (sh->dev_cap.lro_supported) {
/*
* If LRO timeout is not configured by application,
* use the minimal supported value.
*/
- if (!config->lro.timeout)
- config->lro.timeout =
+ if (!config->lro_timeout)
+ config->lro_timeout =
hca_attr->lro_timer_supported_periods[0];
DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
- config->lro.timeout);
- DRV_LOG(DEBUG, "LRO minimal size of TCP segment "
- "required for coalescing is %d bytes",
- hca_attr->lro_min_mss_size);
+ config->lro_timeout);
}
#if defined(HAVE_MLX5DV_DR) && \
(defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \
defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))
if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old &&
- config->dv_flow_en) {
+ sh->config.dv_flow_en) {
uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids;
/*
* Meter needs two REG_C's for color match and pre-sfx
#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */
#if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)
if (hca_attr->log_max_ft_sampler_num > 0 &&
- config->dv_flow_en) {
+ sh->config.dv_flow_en) {
priv->sampler_en = 1;
DRV_LOG(DEBUG, "Sampler enabled!");
} else {
}
#endif
}
- if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 &&
- !(sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) {
- DRV_LOG(WARNING, "Rx CQE 128B compression is not supported");
+ if (config->cqe_comp && !sh->dev_cap.cqe_comp) {
+ DRV_LOG(WARNING, "Rx CQE 128B compression is not supported.");
config->cqe_comp = 0;
}
if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&
}
DRV_LOG(DEBUG, "Rx CQE compression is %ssupported",
config->cqe_comp ? "" : "not ");
- if (config->tx_pp) {
- DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz",
- hca_attr->dev_freq_khz);
- DRV_LOG(DEBUG, "Packet pacing is %ssupported",
- hca_attr->qos.packet_pacing ? "" : "not ");
- DRV_LOG(DEBUG, "Cross channel ops are %ssupported",
- hca_attr->cross_channel ? "" : "not ");
- DRV_LOG(DEBUG, "WQE index ignore is %ssupported",
- hca_attr->wqe_index_ignore ? "" : "not ");
- DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported",
- hca_attr->non_wire_sq ? "" : "not ");
- DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)",
- hca_attr->log_max_static_sq_wq ? "" : "not ",
- hca_attr->log_max_static_sq_wq);
- DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported",
- hca_attr->qos.wqe_rate_pp ? "" : "not ");
- if (!sh->cdev->config.devx) {
- DRV_LOG(ERR, "DevX is required for packet pacing");
- err = ENODEV;
- goto error;
- }
- if (!hca_attr->qos.packet_pacing) {
- DRV_LOG(ERR, "Packet pacing is not supported");
- err = ENODEV;
- goto error;
- }
- if (!hca_attr->cross_channel) {
- DRV_LOG(ERR, "Cross channel operations are"
- " required for packet pacing");
- err = ENODEV;
- goto error;
- }
- if (!hca_attr->wqe_index_ignore) {
- DRV_LOG(ERR, "WQE index ignore feature is"
- " required for packet pacing");
- err = ENODEV;
- goto error;
- }
- if (!hca_attr->non_wire_sq) {
- DRV_LOG(ERR, "Non-wire SQ feature is"
- " required for packet pacing");
- err = ENODEV;
- goto error;
- }
- if (!hca_attr->log_max_static_sq_wq) {
- DRV_LOG(ERR, "Static WQE SQ feature is"
- " required for packet pacing");
- err = ENODEV;
- goto error;
- }
- if (!hca_attr->qos.wqe_rate_pp) {
- DRV_LOG(ERR, "WQE rate mode is required"
- " for packet pacing");
- err = ENODEV;
- goto error;
- }
-#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
- DRV_LOG(ERR, "DevX does not provide UAR offset,"
- " can't create queues for packet pacing");
- err = ENODEV;
- goto error;
-#endif
- }
if (config->std_delay_drop || config->hp_delay_drop) {
if (!hca_attr->rq_delay_drop) {
config->std_delay_drop = 0;
priv->dev_port);
}
}
- if (sh->cdev->config.devx) {
- uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
-
- err = hca_attr->access_register_user ?
- mlx5_devx_cmd_register_read
- (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
- reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
- if (!err) {
- uint32_t ts_mode;
-
- /* MTUTC register is read successfully. */
- ts_mode = MLX5_GET(register_mtutc, reg,
- time_stamp_mode);
- if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
- config->rt_timestamp = 1;
- } else {
- /* Kernel does not support register reading. */
- if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
- config->rt_timestamp = 1;
- }
- }
- /*
- * If HW has bug working with tunnel packet decapsulation and
- * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip
- * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.
- */
- if (hca_attr->scatter_fcs_w_decap_disable && config->decap_en)
- config->hw_fcs_strip = 0;
- DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
- (config->hw_fcs_strip ? "" : "not "));
- if (config->mprq.enabled && !mprq) {
- DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
+ if (config->mprq.enabled && !sh->dev_cap.mprq.enabled) {
+ DRV_LOG(WARNING, "Multi-Packet RQ isn't supported.");
config->mprq.enabled = 0;
}
if (config->max_dump_files_num == 0)
eth_dev->rx_queue_count = mlx5_rx_queue_count;
/* Register MAC address. */
claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
- if (config->vf && config->vf_nl_en)
+ if (sh->dev_cap.vf && sh->config.vf_nl_en)
mlx5_nl_mac_addr_sync(priv->nl_socket_route,
mlx5_ifindex(eth_dev),
eth_dev->data->mac_addrs,
/* Store device configuration on private structure. */
priv->config = *config;
for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
- icfg[i].release_mem_en = !!config->reclaim_mode;
- if (config->reclaim_mode)
+ icfg[i].release_mem_en = !!sh->config.reclaim_mode;
+ if (sh->config.reclaim_mode)
icfg[i].per_core_cache = 0;
priv->flows[i] = mlx5_ipool_create(&icfg[i]);
if (!priv->flows[i])
}
/* Create context for virtual machine VLAN workaround. */
priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
- if (config->dv_flow_en) {
+ if (sh->config.dv_flow_en) {
err = mlx5_alloc_shared_dr(priv);
if (err)
goto error;
if (mlx5_flex_item_port_init(eth_dev) < 0)
goto error;
}
- if (sh->cdev->config.devx && config->dv_flow_en && config->dest_tir) {
+ if (mlx5_devx_obj_ops_en(sh)) {
priv->obj_ops = devx_obj_ops;
mlx5_queue_counter_id_prepare(eth_dev);
priv->obj_ops.lb_dummy_queue_create =
} else {
priv->obj_ops = ibv_obj_ops;
}
- if (config->tx_pp &&
+ if (sh->config.tx_pp &&
priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) {
/*
* HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support
goto error;
}
mlx5_set_metadata_mask(eth_dev);
- if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
+ if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
!priv->sh->dv_regc0_mask) {
DRV_LOG(ERR, "metadata mode %u is not supported "
"(no metadata reg_c[0] is available)",
- priv->config.dv_xmeta_en);
+ sh->config.dv_xmeta_en);
err = ENOTSUP;
goto error;
}
DRV_LOG(DEBUG,
"port %u extensive metadata register is not supported",
eth_dev->data->port_id);
- if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
+ if (sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
DRV_LOG(ERR, "metadata mode %u is not supported "
"(no metadata registers available)",
- priv->config.dv_xmeta_en);
+ sh->config.dv_xmeta_en);
err = ENOTSUP;
goto error;
}
}
- if (priv->config.dv_flow_en &&
- priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
+ if (sh->config.dv_flow_en &&
+ sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
mlx5_flow_ext_mreg_supported(eth_dev) &&
priv->sh->dv_regc0_mask) {
priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
rte_spinlock_init(&priv->shared_act_sl);
mlx5_flow_counter_mode_config(eth_dev);
mlx5_flow_drop_action_config(eth_dev);
- if (priv->config.dv_flow_en)
+ if (sh->config.dv_flow_en)
eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
return eth_dev;
error:
}
static void
-mlx5_os_config_default(struct mlx5_dev_config *config,
- struct mlx5_common_dev_config *cconf)
+mlx5_os_config_default(struct mlx5_dev_config *config)
{
memset(config, 0, sizeof(*config));
config->mps = MLX5_ARG_UNSET;
config->txq_inline_min = MLX5_ARG_UNSET;
config->txq_inline_mpw = MLX5_ARG_UNSET;
config->txqs_inline = MLX5_ARG_UNSET;
- config->vf_nl_en = 1;
config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
- config->mprq.log_min_stride_wqe_size = cconf->devx ?
- cconf->hca_attr.log_min_stride_wqe_sz :
- MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;
- config->dv_esw_en = 1;
- config->dv_flow_en = 1;
- config->decap_en = 1;
config->log_hp_size = MLX5_ARG_UNSET;
- config->allow_duplicate_pattern = 1;
config->std_delay_drop = 0;
config->hp_delay_drop = 0;
}
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
struct mlx5_dev_spawn_data *list = NULL;
struct mlx5_dev_config dev_config;
- unsigned int dev_config_vf;
struct rte_eth_devargs eth_da = *req_eth_da;
struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */
struct mlx5_bond_info bond_info;
* (i.e. master first, then representors from lowest to highest ID).
*/
qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
- /* Device specific configuration. */
- switch (pci_dev->id.device_id) {
- case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
- case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
- dev_config_vf = 1;
- break;
- default:
- dev_config_vf = 0;
- break;
- }
if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) {
/* Set devargs default values. */
if (eth_da.nb_mh_controllers == 0) {
uint32_t restore;
/* Default configuration. */
- mlx5_os_config_default(&dev_config, &cdev->config);
- dev_config.vf = dev_config_vf;
+ mlx5_os_config_default(&dev_config);
list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i],
&dev_config, ð_da);
if (!list[i].eth_dev) {
if (ret != 0)
return ret;
/* Set default config data. */
- mlx5_os_config_default(&config, &cdev->config);
- config.sf = 1;
+ mlx5_os_config_default(&config);
/* Init spawn data. */
spawn.max_port = 1;
spawn.phys_port = 1;
strerror(rte_errno));
return -rte_errno;
}
+ ret = mlx5_probe_again_args_validate(cdev);
+ if (ret) {
+ DRV_LOG(ERR, "Probe again parameters are not compatible : %s",
+ strerror(rte_errno));
+ return -rte_errno;
+ }
if (mlx5_dev_is_pci(cdev->dev))
return mlx5_os_pci_probe(cdev);
else
mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
{
struct mlx5_priv *priv = dev->data->dev_private;
- const int vf = priv->config.vf;
+ const int vf = priv->sh->dev_cap.vf;
if (vf)
mlx5_nl_mac_addr_remove(priv->nl_socket_route,
uint32_t index)
{
struct mlx5_priv *priv = dev->data->dev_private;
- const int vf = priv->config.vf;
+ const int vf = priv->sh->dev_cap.vf;
int ret = 0;
if (vf)
git.droids-corp.org / dpdk.git / blobdiff