#include <errno.h>
#include <rte_malloc.h>
-#include <rte_ethdev_driver.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_driver.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_common.h>
#include <rte_spinlock.h>
#include <rte_string_fns.h>
#include <rte_alarm.h>
+#include <rte_cycles.h>
#include <mlx5_glue.h>
#include <mlx5_devx_cmds.h>
#include <mlx5_common.h>
#include <mlx5_common_os.h>
#include <mlx5_common_mp.h>
-#include <mlx5_common_pci.h>
#include <mlx5_malloc.h>
#include "mlx5_defs.h"
#include "mlx5.h"
#include "mlx5_utils.h"
#include "mlx5_rxtx.h"
+#include "mlx5_rx.h"
+#include "mlx5_tx.h"
#include "mlx5_autoconf.h"
-#include "mlx5_mr.h"
#include "mlx5_flow.h"
+#include "mlx5_flow_os.h"
#include "rte_pmd_mlx5.h"
+#define MLX5_ETH_DRIVER_NAME mlx5_eth
+
+/* Driver type key for new device global syntax. */
+#define MLX5_DRIVER_KEY "driver"
+
/* Device parameter to enable RX completion queue compression. */
#define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
-/* Device parameter to enable RX completion entry padding to 128B. */
-#define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
-
/* Device parameter to enable padding Rx packet to cacheline size. */
#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
/* Decap will be used or not. */
#define MLX5_DECAP_EN "decap_en"
+/* Device parameter to configure allow or prevent duplicate rules pattern. */
+#define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
+
+/* Device parameter to configure implicit registration of mempool memory. */
+#define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
+
/* Shared memory between primary and secondary processes. */
struct mlx5_shared_data *mlx5_shared_data;
static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
LIST_HEAD_INITIALIZER();
-static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
-
+static pthread_mutex_t mlx5_dev_ctx_list_mutex;
static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- {
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+ [MLX5_IPOOL_DECAP_ENCAP] = {
.size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_encap_decap_ipool",
},
- {
+ [MLX5_IPOOL_PUSH_VLAN] = {
.size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_push_vlan_ipool",
},
- {
+ [MLX5_IPOOL_TAG] = {
.size = sizeof(struct mlx5_flow_dv_tag_resource),
.trunk_size = 64,
.grow_trunk = 3,
.grow_shift = 2,
.need_lock = 1,
- .release_mem_en = 1,
+ .release_mem_en = 0,
+ .per_core_cache = (1 << 16),
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_tag_ipool",
},
- {
+ [MLX5_IPOOL_PORT_ID] = {
.size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_port_id_ipool",
},
- {
+ [MLX5_IPOOL_JUMP] = {
.size = sizeof(struct mlx5_flow_tbl_data_entry),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_jump_ipool",
},
- {
+ [MLX5_IPOOL_SAMPLE] = {
.size = sizeof(struct mlx5_flow_dv_sample_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_sample_ipool",
},
- {
+ [MLX5_IPOOL_DEST_ARRAY] = {
.size = sizeof(struct mlx5_flow_dv_dest_array_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_dest_array_ipool",
},
+ [MLX5_IPOOL_TUNNEL_ID] = {
+ .size = sizeof(struct mlx5_flow_tunnel),
+ .trunk_size = MLX5_MAX_TUNNELS,
+ .need_lock = 1,
+ .release_mem_en = 1,
+ .type = "mlx5_tunnel_offload",
+ },
+ [MLX5_IPOOL_TNL_TBL_ID] = {
+ .size = 0,
+ .need_lock = 1,
+ .type = "mlx5_flow_tnl_tbl_ipool",
+ },
#endif
- {
- .size = sizeof(struct mlx5_flow_meter),
+ [MLX5_IPOOL_MTR] = {
+ /**
+ * The ipool index should grow continually from small to big,
+ * for meter idx, so not set grow_trunk to avoid meter index
+ * not jump continually.
+ */
+ .size = sizeof(struct mlx5_legacy_flow_meter),
.trunk_size = 64,
- .grow_trunk = 3,
- .grow_shift = 2,
.need_lock = 1,
.release_mem_en = 1,
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_meter_ipool",
},
- {
+ [MLX5_IPOOL_MCP] = {
.size = sizeof(struct mlx5_flow_mreg_copy_resource),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_mcp_ipool",
},
- {
+ [MLX5_IPOOL_HRXQ] = {
.size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
.trunk_size = 64,
.grow_trunk = 3,
.free = mlx5_free,
.type = "mlx5_hrxq_ipool",
},
- {
+ [MLX5_IPOOL_MLX5_FLOW] = {
/*
* MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
* It set in run time according to PCI function configuration.
.grow_trunk = 3,
.grow_shift = 2,
.need_lock = 1,
- .release_mem_en = 1,
+ .release_mem_en = 0,
+ .per_core_cache = 1 << 19,
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_flow_handle_ipool",
},
- {
+ [MLX5_IPOOL_RTE_FLOW] = {
.size = sizeof(struct rte_flow),
.trunk_size = 4096,
.need_lock = 1,
.free = mlx5_free,
.type = "rte_flow_ipool",
},
+ [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
+ .size = 0,
+ .need_lock = 1,
+ .type = "mlx5_flow_rss_id_ipool",
+ },
+ [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
+ .size = sizeof(struct mlx5_shared_action_rss),
+ .trunk_size = 64,
+ .grow_trunk = 3,
+ .grow_shift = 2,
+ .need_lock = 1,
+ .release_mem_en = 1,
+ .malloc = mlx5_malloc,
+ .free = mlx5_free,
+ .type = "mlx5_shared_action_rss",
+ },
+ [MLX5_IPOOL_MTR_POLICY] = {
+ /**
+ * The ipool index should grow continually from small to big,
+ * for policy idx, so not set grow_trunk to avoid policy index
+ * not jump continually.
+ */
+ .size = sizeof(struct mlx5_flow_meter_sub_policy),
+ .trunk_size = 64,
+ .need_lock = 1,
+ .release_mem_en = 1,
+ .malloc = mlx5_malloc,
+ .free = mlx5_free,
+ .type = "mlx5_meter_policy_ipool",
+ },
};
#define MLX5_FLOW_MIN_ID_POOL_SIZE 512
#define MLX5_ID_GENERATION_ARRAY_FACTOR 16
-#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
+#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
/**
- * Allocate ID pool structure.
+ * Decide whether representor ID is a HPF(host PF) port on BF2.
*
- * @param[in] max_id
- * The maximum id can be allocated from the pool.
+ * @param dev
+ * Pointer to Ethernet device structure.
*
* @return
- * Pointer to pool object, NULL value otherwise.
+ * Non-zero if HPF, otherwise 0.
*/
-struct mlx5_flow_id_pool *
-mlx5_flow_id_pool_alloc(uint32_t max_id)
+bool
+mlx5_is_hpf(struct rte_eth_dev *dev)
{
- struct mlx5_flow_id_pool *pool;
- void *mem;
+ struct mlx5_priv *priv = dev->data->dev_private;
+ uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
+ int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
- pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
- RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
- if (!pool) {
- DRV_LOG(ERR, "can't allocate id pool");
- rte_errno = ENOMEM;
- return NULL;
- }
- mem = mlx5_malloc(MLX5_MEM_ZERO,
- MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
- RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
- if (!mem) {
- DRV_LOG(ERR, "can't allocate mem for id pool");
- rte_errno = ENOMEM;
- goto error;
- }
- pool->free_arr = mem;
- pool->curr = pool->free_arr;
- pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
- pool->base_index = 0;
- pool->max_id = max_id;
- return pool;
-error:
- mlx5_free(pool);
- return NULL;
+ return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
+ MLX5_REPRESENTOR_REPR(-1) == repr;
}
/**
- * Release ID pool structure.
+ * Decide whether representor ID is a SF port representor.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
*
- * @param[in] pool
- * Pointer to flow id pool object to free.
+ * @return
+ * Non-zero if HPF, otherwise 0.
*/
-void
-mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
+bool
+mlx5_is_sf_repr(struct rte_eth_dev *dev)
{
- mlx5_free(pool->free_arr);
- mlx5_free(pool);
+ struct mlx5_priv *priv = dev->data->dev_private;
+ int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
+
+ return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
}
/**
- * Generate ID.
+ * Initialize the ASO aging management structure.
*
- * @param[in] pool
- * Pointer to flow id pool.
- * @param[out] id
- * The generated ID.
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free
*
* @return
- * 0 on success, error value otherwise.
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
*/
-uint32_t
-mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
+int
+mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
{
- if (pool->curr == pool->free_arr) {
- if (pool->base_index == pool->max_id) {
- rte_errno = ENOMEM;
- DRV_LOG(ERR, "no free id");
- return -rte_errno;
- }
- *id = ++pool->base_index;
+ int err;
+
+ if (sh->aso_age_mng)
return 0;
+ sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
+ RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
+ if (!sh->aso_age_mng) {
+ DRV_LOG(ERR, "aso_age_mng allocation was failed.");
+ rte_errno = ENOMEM;
+ return -ENOMEM;
}
- *id = *(--pool->curr);
+ err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
+ if (err) {
+ mlx5_free(sh->aso_age_mng);
+ return -1;
+ }
+ rte_spinlock_init(&sh->aso_age_mng->resize_sl);
+ rte_spinlock_init(&sh->aso_age_mng->free_sl);
+ LIST_INIT(&sh->aso_age_mng->free);
return 0;
}
/**
- * Release ID.
- *
- * @param[in] pool
- * Pointer to flow id pool.
- * @param[out] id
- * The generated ID.
+ * Close and release all the resources of the ASO aging management structure.
*
- * @return
- * 0 on success, error value otherwise.
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free.
*/
-uint32_t
-mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
+static void
+mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
{
- uint32_t size;
- uint32_t size2;
- void *mem;
-
- if (pool->curr == pool->last) {
- size = pool->curr - pool->free_arr;
- size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
- MLX5_ASSERT(size2 > size);
- mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
- SOCKET_ID_ANY);
- if (!mem) {
- DRV_LOG(ERR, "can't allocate mem for id pool");
- rte_errno = ENOMEM;
- return -rte_errno;
+ int i, j;
+
+ mlx5_aso_flow_hit_queue_poll_stop(sh);
+ mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
+ if (sh->aso_age_mng->pools) {
+ struct mlx5_aso_age_pool *pool;
+
+ for (i = 0; i < sh->aso_age_mng->next; ++i) {
+ pool = sh->aso_age_mng->pools[i];
+ claim_zero(mlx5_devx_cmd_destroy
+ (pool->flow_hit_aso_obj));
+ for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
+ if (pool->actions[j].dr_action)
+ claim_zero
+ (mlx5_flow_os_destroy_flow_action
+ (pool->actions[j].dr_action));
+ mlx5_free(pool);
}
- memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
- mlx5_free(pool->free_arr);
- pool->free_arr = mem;
- pool->curr = pool->free_arr + size;
- pool->last = pool->free_arr + size2;
- }
- *pool->curr = id;
- pool->curr++;
- return 0;
+ mlx5_free(sh->aso_age_mng->pools);
+ }
+ mlx5_free(sh->aso_age_mng);
}
/**
age_info = &sh->port[i].age_info;
age_info->flags = 0;
TAILQ_INIT(&age_info->aged_counters);
+ LIST_INIT(&age_info->aged_aso);
rte_spinlock_init(&age_info->aged_sl);
MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
}
static void
mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
{
+ struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
int i;
memset(&sh->cmng, 0, sizeof(sh->cmng));
TAILQ_INIT(&sh->cmng.counters[i]);
rte_spinlock_init(&sh->cmng.csl[i]);
}
+ if (sh->devx && !haswell_broadwell_cpu) {
+ sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
+ sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
+ }
}
/**
LIST_REMOVE(mng, next);
claim_zero(mlx5_devx_cmd_destroy(mng->dm));
- claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
+ claim_zero(mlx5_os_umem_dereg(mng->umem));
mlx5_free(mem);
}
if (cnt->action)
claim_zero
- (mlx5_glue->destroy_flow_action
+ (mlx5_flow_os_destroy_flow_action
(cnt->action));
if (fallback && MLX5_POOL_GET_CNT
(pool, j)->dcs_when_free)
}
/**
- * Initialize the flow resources' indexed mempool.
+ * Initialize the aso flow meters management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free
+ */
+int
+mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
+{
+ if (!sh->mtrmng) {
+ sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
+ sizeof(*sh->mtrmng),
+ RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
+ if (!sh->mtrmng) {
+ DRV_LOG(ERR,
+ "meter management allocation was failed.");
+ rte_errno = ENOMEM;
+ return -ENOMEM;
+ }
+ if (sh->meter_aso_en) {
+ rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
+ LIST_INIT(&sh->mtrmng->pools_mng.meters);
+ }
+ sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
+ }
+ return 0;
+}
+
+/**
+ * Close and release all the resources of
+ * the ASO flow meter management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free.
+ */
+static void
+mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
+{
+ struct mlx5_aso_mtr_pool *mtr_pool;
+ struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
+ uint32_t idx;
+#ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
+ struct mlx5_aso_mtr *aso_mtr;
+ int i;
+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
+
+ if (sh->meter_aso_en) {
+ mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
+ idx = mtrmng->pools_mng.n_valid;
+ while (idx--) {
+ mtr_pool = mtrmng->pools_mng.pools[idx];
+#ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
+ for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
+ aso_mtr = &mtr_pool->mtrs[i];
+ if (aso_mtr->fm.meter_action)
+ claim_zero
+ (mlx5_glue->destroy_flow_action
+ (aso_mtr->fm.meter_action));
+ }
+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
+ claim_zero(mlx5_devx_cmd_destroy
+ (mtr_pool->devx_obj));
+ mtrmng->pools_mng.n_valid--;
+ mlx5_free(mtr_pool);
+ }
+ mlx5_free(sh->mtrmng->pools_mng.pools);
+ }
+ mlx5_free(sh->mtrmng);
+ sh->mtrmng = NULL;
+}
+
+/* Send FLOW_AGED event if needed. */
+void
+mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
+{
+ struct mlx5_age_info *age_info;
+ uint32_t i;
+
+ for (i = 0; i < sh->max_port; i++) {
+ age_info = &sh->port[i].age_info;
+ if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
+ continue;
+ MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
+ if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
+ MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
+ rte_eth_dev_callback_process
+ (&rte_eth_devices[sh->port[i].devx_ih_port_id],
+ RTE_ETH_EVENT_FLOW_AGED, NULL);
+ }
+ }
+}
+
+/*
+ * Initialize the ASO connection tracking structure.
*
* @param[in] sh
* Pointer to mlx5_dev_ctx_shared object.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
+{
+ int err;
+
+ if (sh->ct_mng)
+ return 0;
+ sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
+ RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
+ if (!sh->ct_mng) {
+ DRV_LOG(ERR, "ASO CT management allocation failed.");
+ rte_errno = ENOMEM;
+ return -rte_errno;
+ }
+ err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
+ if (err) {
+ mlx5_free(sh->ct_mng);
+ /* rte_errno should be extracted from the failure. */
+ rte_errno = EINVAL;
+ return -rte_errno;
+ }
+ rte_spinlock_init(&sh->ct_mng->ct_sl);
+ rte_rwlock_init(&sh->ct_mng->resize_rwl);
+ LIST_INIT(&sh->ct_mng->free_cts);
+ return 0;
+}
+
+/*
+ * Close and release all the resources of the
+ * ASO connection tracking management structure.
+ *
+ * @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object to free.
+ */
+static void
+mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
+{
+ struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
+ struct mlx5_aso_ct_pool *ct_pool;
+ struct mlx5_aso_ct_action *ct;
+ uint32_t idx;
+ uint32_t val;
+ uint32_t cnt;
+ int i;
+
+ mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
+ idx = mng->next;
+ while (idx--) {
+ cnt = 0;
+ ct_pool = mng->pools[idx];
+ for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
+ ct = &ct_pool->actions[i];
+ val = __atomic_fetch_sub(&ct->refcnt, 1,
+ __ATOMIC_RELAXED);
+ MLX5_ASSERT(val == 1);
+ if (val > 1)
+ cnt++;
+#ifdef HAVE_MLX5_DR_ACTION_ASO_CT
+ if (ct->dr_action_orig)
+ claim_zero(mlx5_glue->destroy_flow_action
+ (ct->dr_action_orig));
+ if (ct->dr_action_rply)
+ claim_zero(mlx5_glue->destroy_flow_action
+ (ct->dr_action_rply));
+#endif
+ }
+ claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
+ if (cnt) {
+ DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
+ cnt, i);
+ }
+ mlx5_free(ct_pool);
+ /* in case of failure. */
+ mng->next--;
+ }
+ mlx5_free(mng->pools);
+ mlx5_free(mng);
+ /* Management structure must be cleared to 0s during allocation. */
+ sh->ct_mng = NULL;
+}
+
+/**
+ * Initialize the flow resources' indexed mempool.
+ *
* @param[in] sh
+ * Pointer to mlx5_dev_ctx_shared object.
+ * @param[in] config
* Pointer to user dev config.
*/
static void
MLX5_FLOW_HANDLE_VERBS_SIZE;
break;
}
- if (config->reclaim_mode)
+ if (config->reclaim_mode) {
cfg.release_mem_en = 1;
+ cfg.per_core_cache = 0;
+ } else {
+ cfg.release_mem_en = 0;
+ }
sh->ipool[i] = mlx5_ipool_create(&cfg);
}
}
+
/**
* Release the flow resources' indexed mempool.
*
for (i = 0; i < MLX5_IPOOL_MAX; ++i)
mlx5_ipool_destroy(sh->ipool[i]);
+ for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
+ if (sh->mdh_ipools[i])
+ mlx5_ipool_destroy(sh->mdh_ipools[i]);
}
/*
* start after the common header that with the length of a DW(u32).
*/
node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
- prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
+ prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
if (!prf->obj) {
DRV_LOG(ERR, "Failed to create flex parser node object.");
return (rte_errno == 0) ? -ENODEV : -rte_errno;
prf->obj = NULL;
}
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
+{
+ uint32_t sw_parsing_offloads = 0;
+
+ if (attr->swp) {
+ sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
+ if (attr->swp_csum)
+ sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
+
+ if (attr->swp_lso)
+ sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
+ }
+ return sw_parsing_offloads;
+}
+
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
+{
+ uint32_t tn_offloads = 0;
+
+ if (attr->tunnel_stateless_vxlan)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
+ if (attr->tunnel_stateless_gre)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
+ if (attr->tunnel_stateless_geneve_rx)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
+ return tn_offloads;
+}
+
/*
* Allocate Rx and Tx UARs in robust fashion.
* This routine handles the following UAR allocation issues:
*/
static int
mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
- const struct mlx5_dev_config *config)
+ const struct mlx5_common_dev_config *config)
{
uint32_t uar_mapping, retry;
int err = 0;
*/
uar_mapping = 0;
#endif
- sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
+ sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
+ uar_mapping);
#ifdef MLX5DV_UAR_ALLOC_TYPE_NC
if (!sh->tx_uar &&
uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
* the UAR mapping type into account on UAR setup
* on queue creation.
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
- sh->tx_uar = mlx5_glue->devx_alloc_uar
- (sh->ctx, uar_mapping);
+ sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
+ uar_mapping);
} else if (!sh->tx_uar &&
uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
if (config->dbnc == MLX5_TXDB_NCACHED)
* If Verbs/kernel does not support "Non-Cached"
* try the "Write-Combining".
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
- sh->tx_uar = mlx5_glue->devx_alloc_uar
- (sh->ctx, uar_mapping);
+ sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
+ uar_mapping);
}
#endif
if (!sh->tx_uar) {
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
sh->tx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
}
for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
uar_mapping = 0;
- sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
- (sh->ctx, uar_mapping);
+ sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
+ uar_mapping);
#ifdef MLX5DV_UAR_ALLOC_TYPE_NC
if (!sh->devx_rx_uar &&
uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
* should be no datapath noticeable impact,
* can try "Non-Cached" mapping safely.
*/
- DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
- (sh->ctx, uar_mapping);
+ (sh->cdev->ctx, uar_mapping);
}
#endif
if (!sh->devx_rx_uar) {
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
sh->devx_rx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
return err;
}
+/**
+ * rte_mempool_walk() callback to unregister Rx mempools.
+ * It used when implicit mempool registration is disabled.
+ *
+ * @param mp
+ * The mempool being walked.
+ * @param arg
+ * Pointer to the device shared context.
+ */
+static void
+mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
+{
+ struct mlx5_dev_ctx_shared *sh = arg;
+
+ mlx5_dev_mempool_unregister(sh->cdev, mp);
+}
+
+/**
+ * Callback used when implicit mempool registration is disabled
+ * in order to track Rx mempool destruction.
+ *
+ * @param event
+ * Mempool life cycle event.
+ * @param mp
+ * An Rx mempool registered explicitly when the port is started.
+ * @param arg
+ * Pointer to a device shared context.
+ */
+static void
+mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
+ struct rte_mempool *mp, void *arg)
+{
+ struct mlx5_dev_ctx_shared *sh = arg;
+
+ if (event == RTE_MEMPOOL_EVENT_DESTROY)
+ mlx5_dev_mempool_unregister(sh->cdev, mp);
+}
+
+int
+mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
+{
+ struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_dev_ctx_shared *sh = priv->sh;
+ int ret;
+
+ /* Check if we only need to track Rx mempool destruction. */
+ if (!sh->cdev->config.mr_mempool_reg_en) {
+ ret = rte_mempool_event_callback_register
+ (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
+ return ret == 0 || rte_errno == EEXIST ? 0 : ret;
+ }
+ return mlx5_dev_mempool_subscribe(sh->cdev);
+}
+
+/**
+ * Set up multiple TISs with different affinities according to
+ * number of bonding ports
+ *
+ * @param priv
+ * Pointer of shared context.
+ *
+ * @return
+ * Zero on success, -1 otherwise.
+ */
+static int
+mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
+{
+ int i;
+ struct mlx5_devx_lag_context lag_ctx = { 0 };
+ struct mlx5_devx_tis_attr tis_attr = { 0 };
+
+ tis_attr.transport_domain = sh->td->id;
+ if (sh->bond.n_port) {
+ if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
+ sh->lag.tx_remap_affinity[0] =
+ lag_ctx.tx_remap_affinity_1;
+ sh->lag.tx_remap_affinity[1] =
+ lag_ctx.tx_remap_affinity_2;
+ sh->lag.affinity_mode = lag_ctx.port_select_mode;
+ } else {
+ DRV_LOG(ERR, "Failed to query lag affinity.");
+ return -1;
+ }
+ if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
+ for (i = 0; i < sh->bond.n_port; i++) {
+ tis_attr.lag_tx_port_affinity =
+ MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
+ sh->bond.n_port);
+ sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
+ &tis_attr);
+ if (!sh->tis[i]) {
+ DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
+ " %s.", i, sh->bond.n_port,
+ sh->ibdev_name);
+ return -1;
+ }
+ }
+ DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
+ sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
+ lag_ctx.tx_remap_affinity_2);
+ return 0;
+ }
+ if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
+ DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
+ sh->ibdev_name);
+ }
+ tis_attr.lag_tx_port_affinity = 0;
+ sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
+ if (!sh->tis[0]) {
+ DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
+ " %s.", sh->ibdev_name);
+ return -1;
+ }
+ return 0;
+}
+
/**
* Allocate shared device context. If there is multiport device the
* master and representors will share this context, if there is single
*/
struct mlx5_dev_ctx_shared *
mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
- const struct mlx5_dev_config *config)
+ const struct mlx5_dev_config *config)
{
struct mlx5_dev_ctx_shared *sh;
int err = 0;
uint32_t i;
- struct mlx5_devx_tis_attr tis_attr = { 0 };
MLX5_ASSERT(spawn);
/* Secondary process should not create the shared context. */
pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
/* Search for IB context by device name. */
LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
- if (!strcmp(sh->ibdev_name,
- mlx5_os_get_dev_device_name(spawn->phys_dev))) {
+ if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
sh->refcnt++;
goto exit;
}
rte_errno = ENOMEM;
goto exit;
}
- err = mlx5_os_open_device(spawn, config, sh);
- if (!sh->ctx)
- goto error;
- err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
+ pthread_mutex_init(&sh->txpp.mutex, NULL);
+ sh->numa_node = spawn->cdev->dev->numa_node;
+ sh->cdev = spawn->cdev;
+ sh->devx = sh->cdev->config.devx;
+ if (spawn->bond_info)
+ sh->bond = *spawn->bond_info;
+ err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
if (err) {
DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
goto error;
}
sh->refcnt = 1;
sh->max_port = spawn->max_port;
- strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
+ sh->reclaim_mode = config->reclaim_mode;
+ strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
sizeof(sh->ibdev_name) - 1);
- strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
+ strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
sizeof(sh->ibdev_path) - 1);
/*
* Setting port_id to max unallowed value means
sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
}
- sh->pd = mlx5_glue->alloc_pd(sh->ctx);
- if (sh->pd == NULL) {
- DRV_LOG(ERR, "PD allocation failure");
- err = ENOMEM;
- goto error;
- }
if (sh->devx) {
- /* Query the EQN for this core. */
- err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
- if (err) {
- rte_errno = errno;
- DRV_LOG(ERR, "Failed to query event queue number %d.",
- rte_errno);
- goto error;
- }
- err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
- if (err) {
- DRV_LOG(ERR, "Fail to extract pdn from PD");
- goto error;
- }
- sh->td = mlx5_devx_cmd_create_td(sh->ctx);
+ sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
if (!sh->td) {
DRV_LOG(ERR, "TD allocation failure");
err = ENOMEM;
goto error;
}
- tis_attr.transport_domain = sh->td->id;
- sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
- if (!sh->tis) {
+ if (mlx5_setup_tis(sh)) {
DRV_LOG(ERR, "TIS allocation failure");
err = ENOMEM;
goto error;
}
- err = mlx5_alloc_rxtx_uars(sh, config);
+ err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
if (err)
goto error;
MLX5_ASSERT(sh->tx_uar);
MLX5_ASSERT(sh->devx_rx_uar);
MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
}
- sh->flow_id_pool = mlx5_flow_id_pool_alloc
- ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
- if (!sh->flow_id_pool) {
- DRV_LOG(ERR, "can't create flow id pool");
- err = ENOMEM;
- goto error;
- }
#ifndef RTE_ARCH_64
/* Initialize UAR access locks for 32bit implementations. */
rte_spinlock_init(&sh->uar_lock_cq);
for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
rte_spinlock_init(&sh->uar_lock[i]);
#endif
- /*
- * Once the device is added to the list of memory event
- * callback, its global MR cache table cannot be expanded
- * on the fly because of deadlock. If it overflows, lookup
- * should be done by searching MR list linearly, which is slow.
- *
- * At this point the device is not added to the memory
- * event list yet, context is just being created.
- */
- err = mlx5_mr_btree_init(&sh->share_cache.cache,
- MLX5_MR_BTREE_CACHE_N * 2,
- spawn->pci_dev->device.numa_node);
- if (err) {
- err = rte_errno;
- goto error;
- }
- mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
- &sh->share_cache.dereg_mr_cb);
mlx5_os_dev_shared_handler_install(sh);
- sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
- if (!sh->cnt_id_tbl) {
- err = rte_errno;
- goto error;
+ if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
+ err = mlx5_flow_os_init_workspace_once();
+ if (err)
+ goto error;
}
mlx5_flow_aging_init(sh);
mlx5_flow_counters_mng_init(sh);
mlx5_flow_ipool_create(sh, config);
- /* Add device to memory callback list. */
- rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
- LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
- sh, mem_event_cb);
- rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
/* Add context to the global device list. */
LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
+ rte_spinlock_init(&sh->geneve_tlv_opt_sl);
exit:
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
return sh;
pthread_mutex_destroy(&sh->txpp.mutex);
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
MLX5_ASSERT(sh);
- if (sh->cnt_id_tbl)
- mlx5_l3t_destroy(sh->cnt_id_tbl);
- if (sh->tis)
- claim_zero(mlx5_devx_cmd_destroy(sh->tis));
if (sh->td)
claim_zero(mlx5_devx_cmd_destroy(sh->td));
+ i = 0;
+ do {
+ if (sh->tis[i])
+ claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
+ } while (++i < (uint32_t)sh->bond.n_port);
if (sh->devx_rx_uar)
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
if (sh->tx_uar)
mlx5_glue->devx_free_uar(sh->tx_uar);
- if (sh->pd)
- claim_zero(mlx5_glue->dealloc_pd(sh->pd));
- if (sh->ctx)
- claim_zero(mlx5_glue->close_device(sh->ctx));
- if (sh->flow_id_pool)
- mlx5_flow_id_pool_release(sh->flow_id_pool);
mlx5_free(sh);
MLX5_ASSERT(err > 0);
rte_errno = err;
void
mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
{
+ int ret;
+ int i = 0;
+
pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
#ifdef RTE_LIBRTE_MLX5_DEBUG
/* Check the object presence in the list. */
MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
if (--sh->refcnt)
goto exit;
- /* Remove from memory callback device list. */
- rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
- LIST_REMOVE(sh, mem_event_cb);
- rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
- /* Release created Memory Regions. */
- mlx5_mr_release_cache(&sh->share_cache);
+ /* Stop watching for mempool events and unregister all mempools. */
+ if (!sh->cdev->config.mr_mempool_reg_en) {
+ ret = rte_mempool_event_callback_unregister
+ (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
+ if (ret == 0)
+ rte_mempool_walk
+ (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
+ }
/* Remove context from the global device list. */
LIST_REMOVE(sh, next);
+ /* Release resources on the last device removal. */
+ if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
+ mlx5_os_net_cleanup();
+ mlx5_flow_os_release_workspace();
+ }
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
/*
* Ensure there is no async event handler installed.
* Only primary process handles async device events.
**/
mlx5_flow_counters_mng_close(sh);
+ if (sh->aso_age_mng) {
+ mlx5_flow_aso_age_mng_close(sh);
+ sh->aso_age_mng = NULL;
+ }
+ if (sh->mtrmng)
+ mlx5_aso_flow_mtrs_mng_close(sh);
mlx5_flow_ipool_destroy(sh);
mlx5_os_dev_shared_handler_uninstall(sh);
- if (sh->cnt_id_tbl) {
- mlx5_l3t_destroy(sh->cnt_id_tbl);
- sh->cnt_id_tbl = NULL;
- }
if (sh->tx_uar) {
mlx5_glue->devx_free_uar(sh->tx_uar);
sh->tx_uar = NULL;
}
- if (sh->pd)
- claim_zero(mlx5_glue->dealloc_pd(sh->pd));
- if (sh->tis)
- claim_zero(mlx5_devx_cmd_destroy(sh->tis));
+ do {
+ if (sh->tis[i])
+ claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
+ } while (++i < sh->bond.n_port);
if (sh->td)
claim_zero(mlx5_devx_cmd_destroy(sh->td));
if (sh->devx_rx_uar)
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
- if (sh->ctx)
- claim_zero(mlx5_glue->close_device(sh->ctx));
- if (sh->flow_id_pool)
- mlx5_flow_id_pool_release(sh->flow_id_pool);
+ MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
pthread_mutex_destroy(&sh->txpp.mutex);
mlx5_free(sh);
return;
}
/**
- * Destroy table hash list and all the root entries per domain.
+ * Destroy table hash list.
*
* @param[in] priv
* Pointer to the private device data structure.
mlx5_free_table_hash_list(struct mlx5_priv *priv)
{
struct mlx5_dev_ctx_shared *sh = priv->sh;
- struct mlx5_flow_tbl_data_entry *tbl_data;
- union mlx5_flow_tbl_key table_key = {
- {
- .table_id = 0,
- .reserved = 0,
- .domain = 0,
- .direction = 0,
- }
- };
- struct mlx5_hlist_entry *pos;
if (!sh->flow_tbls)
return;
- pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
- if (pos) {
- tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
- entry);
- MLX5_ASSERT(tbl_data);
- mlx5_hlist_remove(sh->flow_tbls, pos);
- mlx5_free(tbl_data);
- }
- table_key.direction = 1;
- pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
- if (pos) {
- tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
- entry);
- MLX5_ASSERT(tbl_data);
- mlx5_hlist_remove(sh->flow_tbls, pos);
- mlx5_free(tbl_data);
- }
- table_key.direction = 0;
- table_key.domain = 1;
- pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
- if (pos) {
- tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
- entry);
- MLX5_ASSERT(tbl_data);
- mlx5_hlist_remove(sh->flow_tbls, pos);
- mlx5_free(tbl_data);
- }
- mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
+ mlx5_hlist_destroy(sh->flow_tbls);
+ sh->flow_tbls = NULL;
}
/**
* Zero on success, positive error code otherwise.
*/
int
-mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
+mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
{
- struct mlx5_dev_ctx_shared *sh = priv->sh;
- char s[MLX5_HLIST_NAMESIZE];
int err = 0;
+ /* Tables are only used in DV and DR modes. */
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+ struct mlx5_dev_ctx_shared *sh = priv->sh;
+ char s[MLX5_NAME_SIZE];
MLX5_ASSERT(sh);
snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
- sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
+ sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
+ false, true, sh,
+ flow_dv_tbl_create_cb,
+ flow_dv_tbl_match_cb,
+ flow_dv_tbl_remove_cb,
+ flow_dv_tbl_clone_cb,
+ flow_dv_tbl_clone_free_cb);
if (!sh->flow_tbls) {
DRV_LOG(ERR, "flow tables with hash creation failed.");
err = ENOMEM;
return err;
}
#ifndef HAVE_MLX5DV_DR
+ struct rte_flow_error error;
+ struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
+
/*
* In case we have not DR support, the zero tables should be created
* because DV expect to see them even if they cannot be created by
* RDMA-CORE.
*/
- union mlx5_flow_tbl_key table_key = {
- {
- .table_id = 0,
- .reserved = 0,
- .domain = 0,
- .direction = 0,
- }
- };
- struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
- sizeof(*tbl_data), 0,
- SOCKET_ID_ANY);
-
- if (!tbl_data) {
- err = ENOMEM;
- goto error;
- }
- tbl_data->entry.key = table_key.v64;
- err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
- if (err)
- goto error;
- __atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);
- table_key.direction = 1;
- tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
- SOCKET_ID_ANY);
- if (!tbl_data) {
- err = ENOMEM;
- goto error;
- }
- tbl_data->entry.key = table_key.v64;
- err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
- if (err)
- goto error;
- __atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);
- table_key.direction = 0;
- table_key.domain = 1;
- tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
- SOCKET_ID_ANY);
- if (!tbl_data) {
+ if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
+ NULL, 0, 1, 0, &error) ||
+ !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
+ NULL, 0, 1, 0, &error) ||
+ !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
+ NULL, 0, 1, 0, &error)) {
err = ENOMEM;
goto error;
}
- tbl_data->entry.key = table_key.v64;
- err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
- if (err)
- goto error;
- __atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);
return err;
error:
mlx5_free_table_hash_list(priv);
#endif /* HAVE_MLX5DV_DR */
+#endif
return err;
}
struct mlx5_proc_priv *ppriv;
size_t ppriv_size;
+ mlx5_proc_priv_uninit(dev);
/*
* UAR register table follows the process private structure. BlueFlame
* registers for Tx queues are stored in the table.
*/
ppriv_size =
sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
- ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
- dev->device->numa_node);
+ ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
+ RTE_CACHE_LINE_SIZE, dev->device->numa_node);
if (!ppriv) {
rte_errno = ENOMEM;
return -rte_errno;
}
- ppriv->uar_table_sz = ppriv_size;
+ ppriv->uar_table_sz = priv->txqs_n;
dev->process_private = ppriv;
return 0;
}
* @param dev
* Pointer to Ethernet device structure.
*/
-static void
+void
mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
{
if (!dev->process_private)
return 0;
DRV_LOG(DEBUG, "port %u closing device \"%s\"",
dev->data->port_id,
- ((priv->sh->ctx != NULL) ?
- mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
+ ((priv->sh->cdev->ctx != NULL) ?
+ mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
/*
* If default mreg copy action is removed at the stop stage,
* the search will return none and nothing will be done anymore.
* If all the flows are already flushed in the device stop stage,
* then this will return directly without any action.
*/
- mlx5_flow_list_flush(dev, &priv->flows, true);
- mlx5_shared_action_flush(dev);
+ mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
+ mlx5_action_handle_flush(dev);
mlx5_flow_meter_flush(dev, NULL);
/* Prevent crashes when queues are still in use. */
dev->rx_pkt_burst = removed_rx_burst;
mlx5_flex_parser_ecpri_release(dev);
if (priv->rxqs != NULL) {
/* XXX race condition if mlx5_rx_burst() is still running. */
- usleep(1000);
+ rte_delay_us_sleep(1000);
for (i = 0; (i != priv->rxqs_n); ++i)
mlx5_rxq_release(dev, i);
priv->rxqs_n = 0;
priv->rxqs = NULL;
}
+ if (priv->representor) {
+ /* Each representor has a dedicated interrupts handler */
+ mlx5_free(dev->intr_handle);
+ dev->intr_handle = NULL;
+ }
if (priv->txqs != NULL) {
/* XXX race condition if mlx5_tx_burst() is still running. */
- usleep(1000);
+ rte_delay_us_sleep(1000);
for (i = 0; (i != priv->txqs_n); ++i)
mlx5_txq_release(dev, i);
priv->txqs_n = 0;
priv->txqs = NULL;
}
mlx5_proc_priv_uninit(dev);
+ if (priv->q_counters) {
+ mlx5_devx_cmd_destroy(priv->q_counters);
+ priv->q_counters = NULL;
+ }
+ if (priv->drop_queue.hrxq)
+ mlx5_drop_action_destroy(dev);
if (priv->mreg_cp_tbl)
- mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
+ mlx5_hlist_destroy(priv->mreg_cp_tbl);
mlx5_mprq_free_mp(dev);
+ if (priv->sh->ct_mng)
+ mlx5_flow_aso_ct_mng_close(priv->sh);
mlx5_os_free_shared_dr(priv);
if (priv->rss_conf.rss_key != NULL)
mlx5_free(priv->rss_conf.rss_key);
if (ret)
DRV_LOG(WARNING, "port %u some flows still remain",
dev->data->port_id);
+ if (priv->hrxqs)
+ mlx5_list_destroy(priv->hrxqs);
/*
* Free the shared context in last turn, because the cleanup
* routines above may use some shared fields, like
unsigned int c = 0;
uint16_t port_id;
- MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
+ MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
struct mlx5_priv *opriv =
rte_eth_devices[port_id].data->dev_private;
return 0;
}
+const struct eth_dev_ops mlx5_dev_ops = {
+ .dev_configure = mlx5_dev_configure,
+ .dev_start = mlx5_dev_start,
+ .dev_stop = mlx5_dev_stop,
+ .dev_set_link_down = mlx5_set_link_down,
+ .dev_set_link_up = mlx5_set_link_up,
+ .dev_close = mlx5_dev_close,
+ .promiscuous_enable = mlx5_promiscuous_enable,
+ .promiscuous_disable = mlx5_promiscuous_disable,
+ .allmulticast_enable = mlx5_allmulticast_enable,
+ .allmulticast_disable = mlx5_allmulticast_disable,
+ .link_update = mlx5_link_update,
+ .stats_get = mlx5_stats_get,
+ .stats_reset = mlx5_stats_reset,
+ .xstats_get = mlx5_xstats_get,
+ .xstats_reset = mlx5_xstats_reset,
+ .xstats_get_names = mlx5_xstats_get_names,
+ .fw_version_get = mlx5_fw_version_get,
+ .dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
+ .read_clock = mlx5_txpp_read_clock,
+ .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
+ .vlan_filter_set = mlx5_vlan_filter_set,
+ .rx_queue_setup = mlx5_rx_queue_setup,
+ .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
+ .tx_queue_setup = mlx5_tx_queue_setup,
+ .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
+ .rx_queue_release = mlx5_rx_queue_release,
+ .tx_queue_release = mlx5_tx_queue_release,
+ .rx_queue_start = mlx5_rx_queue_start,
+ .rx_queue_stop = mlx5_rx_queue_stop,
+ .tx_queue_start = mlx5_tx_queue_start,
+ .tx_queue_stop = mlx5_tx_queue_stop,
+ .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
+ .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
+ .mac_addr_remove = mlx5_mac_addr_remove,
+ .mac_addr_add = mlx5_mac_addr_add,
+ .mac_addr_set = mlx5_mac_addr_set,
+ .set_mc_addr_list = mlx5_set_mc_addr_list,
+ .mtu_set = mlx5_dev_set_mtu,
+ .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
+ .vlan_offload_set = mlx5_vlan_offload_set,
+ .reta_update = mlx5_dev_rss_reta_update,
+ .reta_query = mlx5_dev_rss_reta_query,
+ .rss_hash_update = mlx5_rss_hash_update,
+ .rss_hash_conf_get = mlx5_rss_hash_conf_get,
+ .flow_ops_get = mlx5_flow_ops_get,
+ .rxq_info_get = mlx5_rxq_info_get,
+ .txq_info_get = mlx5_txq_info_get,
+ .rx_burst_mode_get = mlx5_rx_burst_mode_get,
+ .tx_burst_mode_get = mlx5_tx_burst_mode_get,
+ .rx_queue_intr_enable = mlx5_rx_intr_enable,
+ .rx_queue_intr_disable = mlx5_rx_intr_disable,
+ .is_removed = mlx5_is_removed,
+ .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
+ .get_module_info = mlx5_get_module_info,
+ .get_module_eeprom = mlx5_get_module_eeprom,
+ .hairpin_cap_get = mlx5_hairpin_cap_get,
+ .mtr_ops_get = mlx5_flow_meter_ops_get,
+ .hairpin_bind = mlx5_hairpin_bind,
+ .hairpin_unbind = mlx5_hairpin_unbind,
+ .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
+ .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
+ .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
+ .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+ .get_monitor_addr = mlx5_get_monitor_addr,
+};
+
+/* Available operations from secondary process. */
+const struct eth_dev_ops mlx5_dev_sec_ops = {
+ .stats_get = mlx5_stats_get,
+ .stats_reset = mlx5_stats_reset,
+ .xstats_get = mlx5_xstats_get,
+ .xstats_reset = mlx5_xstats_reset,
+ .xstats_get_names = mlx5_xstats_get_names,
+ .fw_version_get = mlx5_fw_version_get,
+ .dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
+ .read_clock = mlx5_txpp_read_clock,
+ .rx_queue_start = mlx5_rx_queue_start,
+ .rx_queue_stop = mlx5_rx_queue_stop,
+ .tx_queue_start = mlx5_tx_queue_start,
+ .tx_queue_stop = mlx5_tx_queue_stop,
+ .rxq_info_get = mlx5_rxq_info_get,
+ .txq_info_get = mlx5_txq_info_get,
+ .rx_burst_mode_get = mlx5_rx_burst_mode_get,
+ .tx_burst_mode_get = mlx5_tx_burst_mode_get,
+ .get_module_info = mlx5_get_module_info,
+ .get_module_eeprom = mlx5_get_module_eeprom,
+};
+
+/* Available operations in flow isolated mode. */
+const struct eth_dev_ops mlx5_dev_ops_isolate = {
+ .dev_configure = mlx5_dev_configure,
+ .dev_start = mlx5_dev_start,
+ .dev_stop = mlx5_dev_stop,
+ .dev_set_link_down = mlx5_set_link_down,
+ .dev_set_link_up = mlx5_set_link_up,
+ .dev_close = mlx5_dev_close,
+ .promiscuous_enable = mlx5_promiscuous_enable,
+ .promiscuous_disable = mlx5_promiscuous_disable,
+ .allmulticast_enable = mlx5_allmulticast_enable,
+ .allmulticast_disable = mlx5_allmulticast_disable,
+ .link_update = mlx5_link_update,
+ .stats_get = mlx5_stats_get,
+ .stats_reset = mlx5_stats_reset,
+ .xstats_get = mlx5_xstats_get,
+ .xstats_reset = mlx5_xstats_reset,
+ .xstats_get_names = mlx5_xstats_get_names,
+ .fw_version_get = mlx5_fw_version_get,
+ .dev_infos_get = mlx5_dev_infos_get,
+ .representor_info_get = mlx5_representor_info_get,
+ .read_clock = mlx5_txpp_read_clock,
+ .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
+ .vlan_filter_set = mlx5_vlan_filter_set,
+ .rx_queue_setup = mlx5_rx_queue_setup,
+ .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
+ .tx_queue_setup = mlx5_tx_queue_setup,
+ .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
+ .rx_queue_release = mlx5_rx_queue_release,
+ .tx_queue_release = mlx5_tx_queue_release,
+ .rx_queue_start = mlx5_rx_queue_start,
+ .rx_queue_stop = mlx5_rx_queue_stop,
+ .tx_queue_start = mlx5_tx_queue_start,
+ .tx_queue_stop = mlx5_tx_queue_stop,
+ .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
+ .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
+ .mac_addr_remove = mlx5_mac_addr_remove,
+ .mac_addr_add = mlx5_mac_addr_add,
+ .mac_addr_set = mlx5_mac_addr_set,
+ .set_mc_addr_list = mlx5_set_mc_addr_list,
+ .mtu_set = mlx5_dev_set_mtu,
+ .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
+ .vlan_offload_set = mlx5_vlan_offload_set,
+ .flow_ops_get = mlx5_flow_ops_get,
+ .rxq_info_get = mlx5_rxq_info_get,
+ .txq_info_get = mlx5_txq_info_get,
+ .rx_burst_mode_get = mlx5_rx_burst_mode_get,
+ .tx_burst_mode_get = mlx5_tx_burst_mode_get,
+ .rx_queue_intr_enable = mlx5_rx_intr_enable,
+ .rx_queue_intr_disable = mlx5_rx_intr_disable,
+ .is_removed = mlx5_is_removed,
+ .get_module_info = mlx5_get_module_info,
+ .get_module_eeprom = mlx5_get_module_eeprom,
+ .hairpin_cap_get = mlx5_hairpin_cap_get,
+ .mtr_ops_get = mlx5_flow_meter_ops_get,
+ .hairpin_bind = mlx5_hairpin_bind,
+ .hairpin_unbind = mlx5_hairpin_unbind,
+ .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
+ .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
+ .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
+ .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+ .get_monitor_addr = mlx5_get_monitor_addr,
+};
+
/**
* Verify and store value for device argument.
*
signed long tmp;
/* No-op, port representors are processed in mlx5_dev_spawn(). */
- if (!strcmp(MLX5_REPRESENTOR, key))
+ if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
+ !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
+ !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
+ !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
return 0;
errno = 0;
tmp = strtol(val, NULL, 0);
}
mod = tmp >= 0 ? tmp : -tmp;
if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
+ if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
+ DRV_LOG(ERR, "invalid CQE compression "
+ "format parameter");
+ rte_errno = EINVAL;
+ return -rte_errno;
+ }
config->cqe_comp = !!tmp;
- } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
- config->cqe_pad = !!tmp;
+ config->cqe_comp_fmt = tmp;
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
} else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
config->mps = !!tmp;
- } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
- if (tmp != MLX5_TXDB_CACHED &&
- tmp != MLX5_TXDB_NCACHED &&
- tmp != MLX5_TXDB_HEURISTIC) {
- DRV_LOG(ERR, "invalid Tx doorbell "
- "mapping parameter");
- rte_errno = EINVAL;
- return -rte_errno;
- }
- config->dbnc = tmp;
} else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
} else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
config->dv_miss_info = 1;
} else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
config->lacp_by_user = !!tmp;
- } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
- config->mr_ext_memseg_en = !!tmp;
} else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
config->max_dump_files_num = tmp;
} else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
config->lro.timeout = tmp;
- } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
+ } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
DRV_LOG(DEBUG, "class argument is %s.", val);
} else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
config->log_hp_size = tmp;
return -rte_errno;
}
config->reclaim_mode = tmp;
- } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
- config->sys_mem_en = !!tmp;
} else if (strcmp(MLX5_DECAP_EN, key) == 0) {
config->decap_en = !!tmp;
+ } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
+ config->allow_duplicate_pattern = !!tmp;
} else {
DRV_LOG(WARNING, "%s: unknown parameter", key);
rte_errno = EINVAL;
mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
{
const char **params = (const char *[]){
+ MLX5_DRIVER_KEY,
MLX5_RXQ_CQE_COMP_EN,
- MLX5_RXQ_CQE_PAD_EN,
MLX5_RXQ_PKT_PAD_EN,
MLX5_RX_MPRQ_EN,
MLX5_RX_MPRQ_LOG_STRIDE_NUM,
MLX5_REPRESENTOR,
MLX5_MAX_DUMP_FILES_NUM,
MLX5_LRO_TIMEOUT_USEC,
- MLX5_CLASS_ARG_NAME,
+ RTE_DEVARGS_KEY_CLASS,
MLX5_HP_BUF_SIZE,
MLX5_RECLAIM_MEM,
MLX5_SYS_MEM_EN,
MLX5_DECAP_EN,
+ MLX5_ALLOW_DUPLICATE_PATTERN,
+ MLX5_MR_MEMPOOL_REG_EN,
NULL,
};
struct rte_kvargs *kvlist;
{
if (config->txq_inline_min != MLX5_ARG_UNSET) {
/* Application defines size of inlined data explicitly. */
- switch (spawn->pci_dev->id.device_id) {
- case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
- case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
- if (config->txq_inline_min <
- (int)MLX5_INLINE_HSIZE_L2) {
- DRV_LOG(DEBUG,
- "txq_inline_mix aligned to minimal"
- " ConnectX-4 required value %d",
- (int)MLX5_INLINE_HSIZE_L2);
- config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
+ if (spawn->pci_dev != NULL) {
+ switch (spawn->pci_dev->id.device_id) {
+ case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
+ case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
+ if (config->txq_inline_min <
+ (int)MLX5_INLINE_HSIZE_L2) {
+ DRV_LOG(DEBUG,
+ "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
+ (int)MLX5_INLINE_HSIZE_L2);
+ config->txq_inline_min =
+ MLX5_INLINE_HSIZE_L2;
+ }
+ break;
}
- break;
}
goto exit;
}
}
}
}
+ if (spawn->pci_dev == NULL) {
+ config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
+ goto exit;
+ }
/*
* We get here if we are unable to deduce
* inline data size with DevX. Try PCI ID
*/
int
mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
- struct mlx5_dev_config *config)
+ struct mlx5_dev_config *config,
+ struct rte_device *dpdk_dev)
{
struct mlx5_dev_ctx_shared *sh = priv->sh;
struct mlx5_dev_config *sh_conf = NULL;
if (sh->refcnt == 1)
return 0;
/* Find the device with shared context. */
- MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
+ MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
struct mlx5_priv *opriv =
rte_eth_devices[port_id].data->dev_private;
*
* @param[in] port_id
* port_id to start looking for device.
- * @param[in] pci_dev
- * Pointer to the hint PCI device. When device is being probed
+ * @param[in] odev
+ * Pointer to the hint device. When device is being probed
* the its siblings (master and preceding representors might
* not have assigned driver yet (because the mlx5_os_pci_probe()
- * is not completed yet, for this case match on hint PCI
+ * is not completed yet, for this case match on hint
* device may be used to detect sibling device.
*
* @return
* port_id of found device, RTE_MAX_ETHPORT if not found.
*/
uint16_t
-mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
+mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
{
while (port_id < RTE_MAX_ETHPORTS) {
struct rte_eth_dev *dev = &rte_eth_devices[port_id];
if (dev->state != RTE_ETH_DEV_UNUSED &&
dev->device &&
- (dev->device == &pci_dev->device ||
+ (dev->device == odev ||
(dev->device->driver &&
dev->device->driver->name &&
- !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
+ ((strcmp(dev->device->driver->name,
+ MLX5_PCI_DRIVER_NAME) == 0) ||
+ (strcmp(dev->device->driver->name,
+ MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
break;
port_id++;
}
}
/**
- * DPDK callback to remove a PCI device.
+ * Callback to remove a device.
*
- * This function removes all Ethernet devices belong to a given PCI device.
+ * This function removes all Ethernet devices belong to a given device.
*
- * @param[in] pci_dev
- * Pointer to the PCI device.
+ * @param[in] cdev
+ * Pointer to the generic device.
*
* @return
* 0 on success, the function cannot fail.
*/
-static int
-mlx5_pci_remove(struct rte_pci_device *pci_dev)
+int
+mlx5_net_remove(struct mlx5_common_device *cdev)
{
uint16_t port_id;
int ret = 0;
- RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
+ RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
/*
* mlx5_dev_close() is not registered to secondary process,
* call the close function explicitly for secondary process.
},
{
RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
- PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
+ PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
},
{
RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
}
};
-static struct mlx5_pci_driver mlx5_driver = {
- .driver_class = MLX5_CLASS_NET,
- .pci_driver = {
- .driver = {
- .name = MLX5_DRIVER_NAME,
- },
- .id_table = mlx5_pci_id_map,
- .probe = mlx5_os_pci_probe,
- .remove = mlx5_pci_remove,
- .dma_map = mlx5_dma_map,
- .dma_unmap = mlx5_dma_unmap,
- .drv_flags = PCI_DRV_FLAGS,
- },
+static struct mlx5_class_driver mlx5_net_driver = {
+ .drv_class = MLX5_CLASS_ETH,
+ .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
+ .id_table = mlx5_pci_id_map,
+ .probe = mlx5_os_net_probe,
+ .remove = mlx5_net_remove,
+ .probe_again = 1,
+ .intr_lsc = 1,
+ .intr_rmv = 1,
};
/* Initialize driver log type. */
-RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
+RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
/**
* Driver initialization routine.
*/
RTE_INIT(rte_mlx5_pmd_init)
{
+ pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
mlx5_common_init();
/* Build the static tables for Verbs conversion. */
mlx5_set_ptype_table();
mlx5_set_cksum_table();
mlx5_set_swp_types_table();
if (mlx5_glue)
- mlx5_pci_driver_register(&mlx5_driver);
+ mlx5_class_driver_register(&mlx5_net_driver);
}
-RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
-RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
-RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
+RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
+RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
+RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");