#include <errno.h>
#include <rte_malloc.h>
-#include <rte_ethdev_driver.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_driver.h>
+#include <ethdev_pci.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#include <rte_common.h>
/* Device parameter to enable RX completion queue compression. */
#define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
-/* Device parameter to enable RX completion entry padding to 128B. */
-#define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
-
/* Device parameter to enable padding Rx packet to cacheline size. */
#define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
* the UAR mapping type into account on UAR setup
* on queue creation.
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->tx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* If Verbs/kernel does not support "Non-Cached"
* try the "Write-Combining".
*/
- DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
+ DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
sh->tx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
sh->tx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
* should be no datapath noticeable impact,
* can try "Non-Cached" mapping safely.
*/
- DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
+ DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
(sh->ctx, uar_mapping);
* IB device context, on context closure all UARs
* will be freed, should be no memory/object leakage.
*/
- DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
+ DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
sh->devx_rx_uar = NULL;
}
/* Check whether we finally succeeded with valid UAR allocation. */
goto error;
}
if (sh->devx) {
- /* Query the EQN for this core. */
- err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
- if (err) {
- rte_errno = errno;
- DRV_LOG(ERR, "Failed to query event queue number %d.",
- rte_errno);
- goto error;
- }
err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
if (err) {
DRV_LOG(ERR, "Fail to extract pdn from PD");
rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
/* Add context to the global device list. */
LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
+ rte_spinlock_init(&sh->geneve_tlv_opt_sl);
exit:
pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
return sh;
mlx5_glue->devx_free_uar(sh->devx_rx_uar);
if (sh->ctx)
claim_zero(mlx5_glue->close_device(sh->ctx));
+ MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
pthread_mutex_destroy(&sh->txpp.mutex);
mlx5_free(sh);
return;
*/
ppriv_size =
sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
- ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
- dev->device->numa_node);
+ ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
+ RTE_CACHE_LINE_SIZE, dev->device->numa_node);
if (!ppriv) {
rte_errno = ENOMEM;
return -rte_errno;
}
- ppriv->uar_table_sz = ppriv_size;
+ ppriv->uar_table_sz = priv->txqs_n;
dev->process_private = ppriv;
return 0;
}
* @param dev
* Pointer to Ethernet device structure.
*/
-static void
+void
mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
{
if (!dev->process_private)
priv->txqs = NULL;
}
mlx5_proc_priv_uninit(dev);
+ if (priv->q_counters) {
+ mlx5_devx_cmd_destroy(priv->q_counters);
+ priv->q_counters = NULL;
+ }
if (priv->drop_queue.hrxq)
mlx5_drop_action_destroy(dev);
if (priv->mreg_cp_tbl)
}
config->cqe_comp = !!tmp;
config->cqe_comp_fmt = tmp;
- } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
- config->cqe_pad = !!tmp;
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
{
const char **params = (const char *[]){
MLX5_RXQ_CQE_COMP_EN,
- MLX5_RXQ_CQE_PAD_EN,
MLX5_RXQ_PKT_PAD_EN,
MLX5_RX_MPRQ_EN,
MLX5_RX_MPRQ_LOG_STRIDE_NUM,