net/mlx5: register memory event callback in Windows

[dpdk.git] / drivers / net / mlx5 / mlx5.c

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 122d4c9..c712fc3 100644 (file)
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -953,6 +953,36 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
        prf->obj = NULL;
 }
 
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
+{
+       uint32_t sw_parsing_offloads = 0;
+
+       if (attr->swp) {
+               sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
+               if (attr->swp_csum)
+                       sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
+
+               if (attr->swp_lso)
+                       sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
+       }
+       return sw_parsing_offloads;
+}
+
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
+{
+       uint32_t tn_offloads = 0;
+
+       if (attr->tunnel_stateless_vxlan)
+               tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
+       if (attr->tunnel_stateless_gre)
+               tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
+       if (attr->tunnel_stateless_geneve_rx)
+               tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
+       return tn_offloads;
+}
+
 /*
  * Allocate Rx and Tx UARs in robust fashion.
  * This routine handles the following UAR allocation issues: