net/mlx5: fix Tx checksum offloads

[dpdk.git] / drivers / net / mlx5 / mlx5.c

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index c0f7b1b..cd66fe1 100644 (file)
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -54,6 +54,7 @@
 #include <rte_ethdev.h>
 #include <rte_ethdev_pci.h>
 #include <rte_pci.h>
+#include <rte_bus_pci.h>
 #include <rte_common.h>
 #include <rte_kvargs.h>
 
@@ -157,7 +158,6 @@ mlx5_alloc_verbs_buf(size_t size, void *data)
        size_t alignment = sysconf(_SC_PAGESIZE);
 
        assert(data != NULL);
-       assert(!mlx5_is_secondary());
        ret = rte_malloc_socket(__func__, size, alignment,
                                priv->dev->device->numa_node);
        DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
@@ -176,7 +176,6 @@ static void
 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 {
        assert(data != NULL);
-       assert(!mlx5_is_secondary());
        DEBUG("Extern free request: %p", ptr);
        rte_free(ptr);
 }
@@ -192,7 +191,7 @@ mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 static void
 mlx5_dev_close(struct rte_eth_dev *dev)
 {
-       struct priv *priv = mlx5_get_priv(dev);
+       struct priv *priv = dev->data->dev_private;
        unsigned int i;
        int ret;
 
@@ -548,6 +547,9 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
        int idx;
        int i;
        struct mlx5dv_context attrs_out;
+#ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
+       struct ibv_counter_set_description cs_desc;
+#endif
 
        (void)pci_drv;
        assert(pci_drv == &mlx5_driver);
@@ -636,15 +638,16 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
         * as all ConnectX-5 devices.
         */
        mlx5dv_query_device(attr_ctx, &attrs_out);
-       if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
-                              MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
-               INFO("Enhanced MPW is detected\n");
-               mps = MLX5_MPW_ENHANCED;
-       } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
-               INFO("MPW is detected\n");
-               mps = MLX5_MPW;
+       if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
+               if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
+                       DEBUG("Enhanced MPW is supported");
+                       mps = MLX5_MPW_ENHANCED;
+               } else {
+                       DEBUG("MPW is supported");
+                       mps = MLX5_MPW;
+               }
        } else {
-               INFO("MPW is disabled\n");
+               DEBUG("MPW isn't supported");
                mps = MLX5_MPW_DISABLED;
        }
        if (RTE_CACHE_LINE_SIZE == 128 &&
@@ -667,6 +670,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                struct ibv_device_attr_ex device_attr_ex;
                struct ether_addr mac;
                uint16_t num_vfs = 0;
+               struct ibv_device_attr_ex device_attr;
                struct mlx5_args args = {
                        .cqe_comp = MLX5_ARG_UNSET,
                        .txq_inline = MLX5_ARG_UNSET,
@@ -681,7 +685,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 
                mlx5_dev[idx].ports |= test;
 
-               if (mlx5_is_secondary()) {
+               if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
                        /* from rte_ethdev.c */
                        char name[RTE_ETH_NAME_MAX_LEN];
 
@@ -721,6 +725,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                        goto port_error;
                }
 
+               ibv_query_device_ex(ctx, NULL, &device_attr);
                /* Check port status. */
                err = ibv_query_port(ctx, port, &port_attr);
                if (err) {
@@ -795,9 +800,16 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
                                         IBV_DEVICE_VXLAN_SUPPORT);
 #endif
-               DEBUG("L2 tunnel checksum offloads are %ssupported",
+               DEBUG("Rx L2 tunnel checksum offloads are %ssupported",
                      (priv->hw_csum_l2tun ? "" : "not "));
 
+#ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
+               priv->counter_set_supported = !!(device_attr.max_counter_sets);
+               ibv_describe_counter_set(ctx, 0, &cs_desc);
+               DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
+                     cs_desc.counter_type, cs_desc.num_of_cs,
+                     cs_desc.attributes);
+#endif
                priv->ind_table_max_size =
                        device_attr_ex.rss_caps.max_rwq_indirection_table_size;
                /* Remove this check once DPDK supports larger/variable
@@ -905,7 +917,6 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                eth_dev->data->mac_addrs = priv->mac;
                eth_dev->device = &pci_dev->device;
                rte_eth_copy_pci_info(eth_dev, pci_dev);
-               eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
                eth_dev->device->driver = &mlx5_driver.driver;
                priv->dev = eth_dev;
                eth_dev->dev_ops = &mlx5_dev_ops;
@@ -1024,8 +1035,6 @@ rte_mlx5_pmd_init(void)
         * using this PMD, which is not supported in forked processes.
         */
        setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
-       /* Don't map UAR to WC if BlueFlame is not used.*/
-       setenv("MLX5_SHUT_UP_BF", "1", 1);
        /* Match the size of Rx completion entry to the size of a cacheline. */
        if (RTE_CACHE_LINE_SIZE == 128)
                setenv("MLX5_CQE_SIZE", "128", 0);