ethdev: remove detachable device flag

[dpdk.git] / drivers / net / mlx5 / mlx5.c

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index e1aa9b9..e3c9b89 100644 (file)
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -101,6 +101,10 @@
 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 #endif
 
+#ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
+#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
+#endif
+
 struct mlx5_args {
        int cqe_comp;
        int txq_inline;
@@ -539,10 +543,14 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
        struct ibv_device_attr_ex device_attr;
        unsigned int sriov;
        unsigned int mps;
+       unsigned int cqe_comp;
        unsigned int tunnel_en = 0;
        int idx;
        int i;
        struct mlx5dv_context attrs_out;
+#ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
+       struct ibv_counter_set_description cs_desc;
+#endif
 
        (void)pci_drv;
        assert(pci_drv == &mlx5_driver);
@@ -631,17 +639,23 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
         * as all ConnectX-5 devices.
         */
        mlx5dv_query_device(attr_ctx, &attrs_out);
-       if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
-                              MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
-               INFO("Enhanced MPW is detected\n");
-               mps = MLX5_MPW_ENHANCED;
-       } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
-               INFO("MPW is detected\n");
-               mps = MLX5_MPW;
+       if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
+               if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
+                       DEBUG("Enhanced MPW is supported");
+                       mps = MLX5_MPW_ENHANCED;
+               } else {
+                       DEBUG("MPW is supported");
+                       mps = MLX5_MPW;
+               }
        } else {
-               INFO("MPW is disabled\n");
+               DEBUG("MPW isn't supported");
                mps = MLX5_MPW_DISABLED;
        }
+       if (RTE_CACHE_LINE_SIZE == 128 &&
+           !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
+               cqe_comp = 0;
+       else
+               cqe_comp = 1;
        if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
                goto error;
        INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
@@ -657,6 +671,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                struct ibv_device_attr_ex device_attr_ex;
                struct ether_addr mac;
                uint16_t num_vfs = 0;
+               struct ibv_device_attr_ex device_attr;
                struct mlx5_args args = {
                        .cqe_comp = MLX5_ARG_UNSET,
                        .txq_inline = MLX5_ARG_UNSET,
@@ -711,6 +726,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                        goto port_error;
                }
 
+               ibv_query_device_ex(ctx, NULL, &device_attr);
                /* Check port status. */
                err = ibv_query_port(ctx, port, &port_attr);
                if (err) {
@@ -758,7 +774,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                priv->pd = pd;
                priv->mtu = ETHER_MTU;
                priv->mps = mps; /* Enable MPW by default if supported. */
-               priv->cqe_comp = 1; /* Enable compression by default. */
+               priv->cqe_comp = cqe_comp;
                priv->tunnel_en = tunnel_en;
                /* Enable vector by default if supported. */
                priv->tx_vec_en = 1;
@@ -788,6 +804,13 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                DEBUG("L2 tunnel checksum offloads are %ssupported",
                      (priv->hw_csum_l2tun ? "" : "not "));
 
+#ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
+               priv->counter_set_supported = !!(device_attr.max_counter_sets);
+               ibv_describe_counter_set(ctx, 0, &cs_desc);
+               DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
+                     cs_desc.counter_type, cs_desc.num_of_cs,
+                     cs_desc.attributes);
+#endif
                priv->ind_table_max_size =
                        device_attr_ex.rss_caps.max_rwq_indirection_table_size;
                /* Remove this check once DPDK supports larger/variable
@@ -847,6 +870,10 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                                priv->txq_inline = MLX5_WQE_SIZE_MAX -
                                                   MLX5_WQE_SIZE;
                }
+               if (priv->cqe_comp && !cqe_comp) {
+                       WARN("Rx CQE compression isn't supported");
+                       priv->cqe_comp = 0;
+               }
                /* Configure the first MAC address by default. */
                if (priv_get_mac(priv, &mac.addr_bytes)) {
                        ERROR("cannot get MAC address, is mlx5_en loaded?"
@@ -891,7 +918,6 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
                eth_dev->data->mac_addrs = priv->mac;
                eth_dev->device = &pci_dev->device;
                rte_eth_copy_pci_info(eth_dev, pci_dev);
-               eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
                eth_dev->device->driver = &mlx5_driver.driver;
                priv->dev = eth_dev;
                eth_dev->dev_ops = &mlx5_dev_ops;