#include <mlx5_common_mp.h>
#include <mlx5_common_mr.h>
#include <mlx5_common_devx.h>
+#include <mlx5_common_defs.h>
#include "mlx5_defs.h"
#include "mlx5_utils.h"
#include "mlx5_os.h"
#include "mlx5_autoconf.h"
-
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+#include "mlx5_dr.h"
+#endif
#define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
#define MLX5_MAX_MODIFY_NUM 32
#define MLX5_ROOT_TBL_MODIFY_NUM 16
+/* Maximal number of flex items created on the port.*/
+#define MLX5_PORT_FLEX_ITEM_NUM 4
+
+/* Maximal number of field/field parts to map into sample registers .*/
+#define MLX5_FLEX_ITEM_MAPPING_NUM 32
+
enum mlx5_ipool_index {
#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
MLX5_IPOOL_TAG, /* Pool for tag resource. */
MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
- MLX5_IPOOL_JUMP, /* Pool for jump resource. */
+ MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */
+ /* Pool for HWS group. Jump action will be created internally. */
+ MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP,
MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
MLX5_FLOW_TYPE_MAXI,
};
+/* The mode of delay drop for Rx queues. */
+enum mlx5_delay_drop_mode {
+ MLX5_DELAY_DROP_NONE = 0, /* All disabled. */
+ MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */
+ MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */
+};
+
+/* The HWS action type root/non-root. */
+enum mlx5_hw_action_flag_type {
+ MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */
+ MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */
+ MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */
+};
+
/* Hlist and list callback context. */
struct mlx5_flow_cb_ctx {
struct rte_eth_dev *dev;
void *data2;
};
-/* Device attributes used in mlx5 PMD */
-struct mlx5_dev_attr {
- uint64_t device_cap_flags_ex;
- int max_qp_wr;
- int max_sge;
- int max_cq;
- int max_qp;
- int max_cqe;
- uint32_t max_pd;
- uint32_t max_mr;
- uint32_t max_srq;
- uint32_t max_srq_wr;
- uint32_t raw_packet_caps;
- uint32_t max_rwq_indirection_table_size;
- uint32_t max_tso;
- uint32_t tso_supported_qpts;
- uint64_t flags;
- uint64_t comp_mask;
- uint32_t sw_parsing_offloads;
- uint32_t min_single_stride_log_num_of_bytes;
- uint32_t max_single_stride_log_num_of_bytes;
- uint32_t min_single_wqe_log_num_of_strides;
- uint32_t max_single_wqe_log_num_of_strides;
- uint32_t stride_supported_qpts;
- uint32_t tunnel_offloads_caps;
- char fw_ver[64];
+/* Device capabilities structure which isn't changed in any stage. */
+struct mlx5_dev_cap {
+ int max_cq; /* Maximum number of supported CQs */
+ int max_qp; /* Maximum number of supported QPs. */
+ int max_qp_wr; /* Maximum number of outstanding WR on any WQ. */
+ int max_sge;
+ /* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read
+ * operations.
+ */
+ int mps; /* Multi-packet send supported mode. */
+ uint32_t vf:1; /* This is a VF. */
+ uint32_t sf:1; /* This is a SF. */
+ uint32_t txpp_en:1; /* Tx packet pacing is supported. */
+ uint32_t mpls_en:1; /* MPLS over GRE/UDP is supported. */
+ uint32_t cqe_comp:1; /* CQE compression is supported. */
+ uint32_t hw_csum:1; /* Checksum offload is supported. */
+ uint32_t hw_padding:1; /* End alignment padding is supported. */
+ uint32_t dest_tir:1; /* Whether advanced DR API is available. */
+ uint32_t dv_esw_en:1; /* E-Switch DV flow is supported. */
+ uint32_t dv_flow_en:1; /* DV flow is supported. */
+ uint32_t swp:3; /* Tx generic tunnel checksum and TSO offload. */
+ uint32_t hw_vlan_strip:1; /* VLAN stripping is supported. */
+ uint32_t scatter_fcs_w_decap_disable:1;
+ /* HW has bug working with tunnel packet decap and scatter FCS. */
+ uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */
+ uint32_t rt_timestamp:1; /* Realtime timestamp format. */
+ uint32_t lro_supported:1; /* Whether LRO is supported. */
+ uint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */
+ uint32_t tunnel_en:3;
+ /* Whether tunnel stateless offloads are supported. */
+ uint32_t ind_table_max_size;
+ /* Maximum receive WQ indirection table size. */
+ uint32_t tso:1; /* Whether TSO is supported. */
+ uint32_t tso_max_payload_sz; /* Maximum TCP payload for TSO. */
+ struct {
+ uint32_t enabled:1; /* Whether MPRQ is enabled. */
+ uint32_t log_min_stride_size; /* Log min size of a stride. */
+ uint32_t log_max_stride_size; /* Log max size of a stride. */
+ uint32_t log_min_stride_num; /* Log min num of strides. */
+ uint32_t log_max_stride_num; /* Log max num of strides. */
+ uint32_t log_min_stride_wqe_size;
+ /* Log min WQE size, (size of single stride)*(num of strides).*/
+ } mprq; /* Capability for Multi-Packet RQ. */
+ char fw_ver[64]; /* Firmware version of this device. */
};
/** Data associated with devices to spawn. */
uint32_t max_port; /**< Device maximal port index. */
uint32_t phys_port; /**< Device physical port index. */
int pf_bond; /**< bonding device PF index. < 0 - no bonding */
- int numa_node; /**< Device numa node. */
struct mlx5_switch_info info; /**< Switch information. */
- void *phys_dev; /**< Associated physical device. */
+ const char *phys_dev_name; /**< Name of physical device. */
struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
struct rte_pci_device *pci_dev; /**< Backend PCI device. */
+ struct mlx5_common_device *cdev; /**< Backend common device. */
struct mlx5_bond_info *bond_info;
};
int rc; /**< Return code. */
};
-/** Key string for IPC. */
-#define MLX5_MP_NAME "net_mlx5_mp"
-
-
LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
/* Shared data between primary and secondary processes. */
/* Global spinlock for primary and secondary processes. */
int init_done; /* Whether primary has done initialization. */
unsigned int secondary_cnt; /* Number of secondary processes init'd. */
- struct mlx5_dev_list mem_event_cb_list;
- rte_rwlock_t mem_event_rwlock;
};
/* Per-process data structure, not visible to other processes. */
uint64_t imissed;
};
-/* Default PMD specific parameter value. */
-#define MLX5_ARG_UNSET (-1)
-
-#define MLX5_LRO_SUPPORTED(dev) \
- (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
-
/* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
#define MLX5_LRO_SEG_CHUNK_SIZE 256u
/* Maximal number of segments to split. */
#define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS)
-/* LRO configurations structure. */
-struct mlx5_lro_config {
- uint32_t supported:1; /* Whether LRO is supported. */
- uint32_t timeout; /* User configuration. */
-};
-
/*
- * Device configuration structure.
- *
- * Merged configuration from:
- *
- * - Device capabilities,
- * - User device parameters disabled features.
+ * Port configuration structure.
+ * User device parameters disabled features.
+ * This structure contains all configurations coming from devargs which
+ * oriented to port. When probing again, devargs doesn't have to be compatible
+ * with primary devargs. It is updated for each port in spawn function.
*/
-struct mlx5_dev_config {
- unsigned int hw_csum:1; /* Checksum offload is supported. */
- unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
+struct mlx5_port_config {
unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
- unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
unsigned int hw_padding:1; /* End alignment padding is supported. */
- unsigned int vf:1; /* This is a VF. */
- unsigned int sf:1; /* This is a SF. */
- unsigned int tunnel_en:1;
- /* Whether tunnel stateless offloads are supported. */
- unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
unsigned int cqe_comp:1; /* CQE compression is enabled. */
unsigned int cqe_comp_fmt:3; /* CQE compression format. */
- unsigned int tso:1; /* Whether TSO is supported. */
unsigned int rx_vec_en:1; /* Rx vector is enabled. */
- unsigned int mr_ext_memseg_en:1;
- /* Whether memseg should be extended for MR creation. */
- unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
- unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
- unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
- unsigned int dv_flow_en:1; /* Enable DV flow. */
- unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
- unsigned int lacp_by_user:1;
- /* Enable user to manage LACP traffic. */
- unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
- unsigned int devx:1; /* Whether devx interface is available or not. */
- unsigned int dest_tir:1; /* Whether advanced DR API is available. */
- unsigned int reclaim_mode:2; /* Memory reclaim mode. */
- unsigned int rt_timestamp:1; /* realtime timestamp format. */
- unsigned int sys_mem_en:1; /* The default memory allocator. */
- unsigned int decap_en:1; /* Whether decap will be used or not. */
- unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
- unsigned int allow_duplicate_pattern:1;
- /* Allow/Prevent the duplicate rules pattern. */
+ unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */
+ unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */
struct {
unsigned int enabled:1; /* Whether MPRQ is enabled. */
- unsigned int stride_num_n; /* Number of strides. */
- unsigned int stride_size_n; /* Size of a stride. */
- unsigned int min_stride_size_n; /* Min size of a stride. */
- unsigned int max_stride_size_n; /* Max size of a stride. */
+ unsigned int log_stride_num; /* Log number of strides. */
+ unsigned int log_stride_size; /* Log size of a stride. */
unsigned int max_memcpy_len;
/* Maximum packet size to memcpy Rx packets. */
unsigned int min_rxqs_num;
/* Rx queue count threshold to enable MPRQ. */
} mprq; /* Configurations for Multi-Packet RQ. */
int mps; /* Multi-packet send supported mode. */
- int dbnc; /* Skip doorbell register write barrier. */
- unsigned int flow_prio; /* Number of flow priorities. */
- enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
- /* Availibility of mreg_c's. */
- unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
- unsigned int ind_table_max_size; /* Maximum indirection table size. */
unsigned int max_dump_files_num; /* Maximum dump files per queue. */
unsigned int log_hp_size; /* Single hairpin queue data size in total. */
+ unsigned int lro_timeout; /* LRO user configuration. */
int txqs_inline; /* Queue number threshold for inlining. */
int txq_inline_min; /* Minimal amount of data bytes to inline. */
int txq_inline_max; /* Max packet size for inlining with SEND. */
int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
+};
+
+/*
+ * Share context device configuration structure.
+ * User device parameters disabled features.
+ * This structure updated once for device in mlx5_alloc_shared_dev_ctx()
+ * function and cannot change even when probing again.
+ */
+struct mlx5_sh_config {
int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */
int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
- struct mlx5_hca_attr hca_attr; /* HCA attributes. */
- struct mlx5_lro_config lro; /* LRO configuration. */
+ uint32_t reclaim_mode:2; /* Memory reclaim mode. */
+ uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */
+ /* Enable DV flow. 1 means SW steering, 2 means HW steering. */
+ unsigned int dv_flow_en:2;
+ uint32_t dv_xmeta_en:2; /* Enable extensive flow metadata. */
+ uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */
+ uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
+ uint32_t vf_nl_en:1; /* Enable Netlink requests in VF mode. */
+ uint32_t lacp_by_user:1; /* Enable user to manage LACP traffic. */
+ uint32_t decap_en:1; /* Whether decap will be used or not. */
+ uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */
+ uint32_t allow_duplicate_pattern:1;
+ /* Allow/Prevent the duplicate rules pattern. */
};
/* Flow drop context necessary due to Verbs API. */
struct mlx5_drop {
struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
- struct mlx5_rxq_obj *rxq; /* Rx queue object. */
+ struct mlx5_rxq_priv *rxq; /* Rx queue. */
};
/* Loopback dummy queue resources required due to Verbs API. */
uint16_t refcnt; /* Reference count for representors. */
};
+/* HW steering queue job descriptor type. */
+enum {
+ MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */
+ MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */
+};
+
+/* HW steering flow management job descriptor. */
+struct mlx5_hw_q_job {
+ uint32_t type; /* Job type. */
+ struct rte_flow_hw *flow; /* Flow attached to the job. */
+ void *user_data; /* Job user data. */
+ uint8_t *encap_data; /* Encap data. */
+};
+
+/* HW steering job descriptor LIFO pool. */
+struct mlx5_hw_q {
+ uint32_t job_idx; /* Free job index. */
+ uint32_t size; /* LIFO size. */
+ struct mlx5_hw_q_job **job; /* LIFO header. */
+} __rte_cache_aligned;
+
#define MLX5_COUNTERS_PER_POOL 512
#define MLX5_MAX_PENDING_QUERIES 4
#define MLX5_CNT_CONTAINER_RESIZE 64
#define MLX5_CNT_SHARED_OFFSET 0x80000000
-#define IS_LEGACY_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
#define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
MLX5_CNT_BATCH_OFFSET)
#define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
#define MLX5_CNT_ARRAY_IDX(pool, cnt) \
((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
MLX5_CNT_LEN(pool)))
+#define MLX5_TS_MASK_SECS 8ull
+/* timestamp wrapping in seconds, must be power of 2. */
+
/*
* The pool index and offset of counter in the pool array makes up the
* counter index. In case the counter is from pool 0 and offset 0, it
};
};
-/* Shared counter configuration. */
-struct mlx5_shared_counter_conf {
- struct rte_eth_dev *dev; /* The device shared counter belongs to. */
- uint32_t id; /* The shared counter ID. */
-};
-
struct mlx5_flow_counter_pool;
/* Generic counters information. */
struct mlx5_flow_counter {
struct mlx5_counter_stats_mem_mng {
LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
struct mlx5_counter_stats_raw *raws;
- struct mlx5_devx_obj *dm;
- void *umem;
+ struct mlx5_pmd_wrapped_mr wm;
};
/* Raw memory structure for the counter statistics values of a pool. */
uint8_t pending_queries;
uint16_t pool_index;
uint8_t query_thread_on;
- bool relaxed_ordering_read;
- bool relaxed_ordering_write;
bool counter_fallback; /* Use counter fallback management. */
LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
rte_spinlock_t sqsl;
struct mlx5_aso_cq cq;
struct mlx5_devx_sq sq_obj;
- volatile uint64_t *uar_addr;
struct mlx5_pmd_mr mr;
uint16_t pi;
uint32_t head;
struct mlx5_aso_age_pool **pools;
uint16_t n; /* Total number of pools. */
uint16_t next; /* Number of pools in use, index of next free pool. */
- rte_spinlock_t resize_sl; /* Lock for resize objects. */
+ rte_rwlock_t resize_rwl; /* Lock for resize objects. */
rte_spinlock_t free_sl; /* Lock for free list access. */
struct aso_age_list free; /* Free age actions list - ready to use. */
struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
struct mlx5_dev_shared_port {
uint32_t ih_port_id;
uint32_t devx_ih_port_id;
+ uint32_t nl_ih_port_id;
/*
* Interrupt handler port_id. Used by shared interrupt
* handler to find the corresponding rte_eth device
#define MLX5_MTR_TABLE_ID_DROP 2
/* Priority of the meter policy matcher. */
#define MLX5_MTR_POLICY_MATCHER_PRIO 0
+/* Green & yellow color valid for now. */
+#define MLX5_MTR_POLICY_MODE_ALL 0
/* Default policy. */
#define MLX5_MTR_POLICY_MODE_DEF 1
/* Only green color valid. */
/* If yellow color policy is skipped. */
uint32_t skip_g:1;
/* If green color policy is skipped. */
+ uint32_t mark:1;
+ /* If policy contains mark action. */
rte_spinlock_t sl;
uint32_t ref_cnt;
/* Use count. */
volatile uint16_t n_valid; /* Number of valid pools. */
uint16_t n; /* Number of pools. */
rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */
+ rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */
struct aso_meter_list meters; /* Free ASO flow meter list. */
struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */
struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */
/* Table structure. */
struct mlx5_flow_tbl_resource {
void *obj; /**< Pointer to DR table object. */
- uint32_t refcnt; /**< Reference counter. */
};
#define MLX5_MAX_TABLES UINT16_MAX
uint32_t base_index;
/**< The next index that can be used without any free elements. */
uint32_t *curr; /**< Pointer to the index to pop. */
- uint32_t *last; /**< Pointer to the last element in the empty arrray. */
+ uint32_t *last; /**< Pointer to the last element in the empty array. */
uint32_t max_id; /**< Maximum id can be allocated from the pool. */
};
uint32_t tick; /* Completion tick duration in nanoseconds. */
uint32_t test; /* Packet pacing test mode. */
int32_t skew; /* Scheduling skew. */
- struct rte_intr_handle intr_handle; /* Periodic interrupt. */
+ struct rte_intr_handle *intr_handle; /* Periodic interrupt. */
void *echan; /* Event Channel. */
struct mlx5_txpp_wq clock_queue; /* Clock Queue. */
struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */
void *pp; /* Packet pacing context. */
uint16_t pp_id; /* Packet pacing context index. */
uint16_t ts_n; /* Number of captured timestamps. */
- uint16_t ts_p; /* Pointer to statisticks timestamp. */
+ uint16_t ts_p; /* Pointer to statistics timestamp. */
struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */
struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */
uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */
uint64_t err_ts_future; /* Timestamp in the distant future. */
};
-/* Supported flex parser profile ID. */
-enum mlx5_flex_parser_profile_id {
- MLX5_FLEX_PARSER_ECPRI_0 = 0,
- MLX5_FLEX_PARSER_MAX = 8,
-};
-
-/* Sample ID information of flex parser structure. */
-struct mlx5_flex_parser_profiles {
+/* Sample ID information of eCPRI flex parser structure. */
+struct mlx5_ecpri_parser_profile {
uint32_t num; /* Actual number of samples. */
uint32_t ids[8]; /* Sample IDs for this profile. */
uint8_t offset[8]; /* Bytes offset of each parser. */
struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
};
+/* LAG attr. */
+struct mlx5_lag {
+ uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */
+ uint8_t affinity_mode; /* TIS or hash based affinity */
+};
+
+/* DevX flex parser context. */
+struct mlx5_flex_parser_devx {
+ struct mlx5_list_entry entry; /* List element at the beginning. */
+ uint32_t num_samples;
+ void *devx_obj;
+ struct mlx5_devx_graph_node_attr devx_conf;
+ uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM];
+};
+
+/* Pattern field descriptor - how to translate flex pattern into samples. */
+__extension__
+struct mlx5_flex_pattern_field {
+ uint16_t width:6;
+ uint16_t shift:5;
+ uint16_t reg_id:5;
+};
+#define MLX5_INVALID_SAMPLE_REG_ID 0x1F
+
+/* Port flex item context. */
+struct mlx5_flex_item {
+ struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */
+ uint32_t refcnt; /* Atomically accessed refcnt by flows. */
+ enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */
+ uint32_t mapnum; /* Number of pattern translation entries. */
+ struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM];
+};
+
/*
* Shared Infiniband device context for Master/Representors
* which belong to same IB device with multiple IB ports.
struct mlx5_dev_ctx_shared {
LIST_ENTRY(mlx5_dev_ctx_shared) next;
uint32_t refcnt;
- uint32_t devx:1; /* Opened with DV. */
+ uint32_t esw_mode:1; /* Whether is E-Switch mode. */
uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
- uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
- uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
uint32_t steering_format_version:4;
/* Indicates the device steering logic format. */
- uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+ uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
- uint32_t reclaim_mode:1; /* Reclaim memory. */
+ uint32_t dr_drop_action_en:1; /* Use DR drop action. */
+ uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */
+ uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */
+ uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */
uint32_t max_port; /* Maximal IB device port index. */
struct mlx5_bond_info bond; /* Bonding information. */
- void *ctx; /* Verbs/DV/DevX context. */
- void *pd; /* Protection Domain. */
- uint32_t pdn; /* Protection Domain number. */
+ struct mlx5_common_device *cdev; /* Backend mlx5 device. */
uint32_t tdn; /* Transport Domain number. */
char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
- struct mlx5_dev_attr device_attr; /* Device properties. */
+ struct mlx5_dev_cap dev_cap; /* Device capabilities. */
+ struct mlx5_sh_config config; /* Device configuration. */
int numa_node; /* Numa node of backing physical device. */
- LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
- /**< Called by memory event callback. */
- struct mlx5_mr_share_cache share_cache;
/* Packet pacing related structure. */
struct mlx5_dev_txpp txpp;
/* Shared DV/DR flow data section. */
uint32_t dv_meta_mask; /* flow META metadata supported mask. */
uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
- uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
+ uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */
void *fdb_domain; /* FDB Direct Rules name space handle. */
void *rx_domain; /* RX Direct Rules name space handle. */
void *tx_domain; /* TX Direct Rules name space handle. */
#ifndef RTE_ARCH_64
- rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
+ rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */
rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
/* UAR same-page access control required in 32bit implementations. */
#endif
- struct mlx5_hlist *flow_tbls;
+ union {
+ struct mlx5_hlist *flow_tbls; /* SWS flow table. */
+ struct mlx5_hlist *groups; /* HWS flow group. */
+ };
struct mlx5_flow_tunnel_hub *tunnel_hub;
/* Direct Rules tables for FDB, NIC TX+RX */
void *dr_drop_action; /* Pointer to DR drop action, any domain. */
struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */
struct mlx5_list *sample_action_list; /* List of sample actions. */
struct mlx5_list *dest_array_list;
+ struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */
/* List of destination array actions. */
struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
void *default_miss_action; /* Default miss action. */
struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM];
- /* Memory Pool for mlx5 flow resources. */
- struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
/* Shared interrupt handler section. */
- struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
- struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
+ struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */
+ struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */
+ struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */
void *devx_comp; /* DEVX async comp obj. */
- struct mlx5_devx_obj *tis; /* TIS object. */
+ struct mlx5_devx_obj *tis[16]; /* TIS object. */
struct mlx5_devx_obj *td; /* Transport domain. */
- void *tx_uar; /* Tx/packet pacing shared UAR. */
- struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
+ struct mlx5_lag lag; /* LAG attributes */
+ struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */
+ struct mlx5_uar rx_uar; /* DevX UAR for Rx. */
+ struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */
+ struct mlx5_ecpri_parser_profile ecpri_parser;
/* Flex parser profiles information. */
- void *devx_rx_uar; /* DevX UAR for Rx. */
+ LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */
struct mlx5_aso_age_mng *aso_age_mng;
/* Management data for aging mechanism using ASO Flow Hit. */
struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
struct mlx5_aso_ct_pools_mng *ct_mng;
/* Management data for ASO connection tracking. */
struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */
+ unsigned int flow_max_priority;
+ enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
+ /* Availability of mreg_c's. */
struct mlx5_dev_shared_port port[]; /* per device port data array. */
};
struct mlx5_proc_priv {
size_t uar_table_sz;
/* Size of UAR register table. */
- void *uar_table[];
+ struct mlx5_uar_data uar_table[];
/* Table of UAR registers for each process. */
};
struct mlx5_flow_rss_desc {
uint32_t level;
uint32_t queue_num; /**< Number of entries in @p queue. */
- uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
+ uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */
uint64_t hash_fields; /* Verbs Hash fields. */
uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
uint32_t key_len; /**< RSS hash key len. */
+ uint32_t hws_flags; /**< HW steering action. */
uint32_t tunnel; /**< Queue in tunnel. */
uint32_t shared_rss; /**< Shared RSS index. */
struct mlx5_ind_table_obj *ind_tbl;
};
struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
struct {
- struct mlx5_devx_rq rq_obj; /* DevX RQ object. */
+ struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */
struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
void *devx_channel;
};
#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
void *action; /* DV QP action pointer. */
#endif
+ uint32_t hws_flags; /* Hw steering flags. */
uint64_t hash_fields; /* Verbs Hash fields. */
uint32_t rss_key_len; /* Hash key length in bytes. */
uint32_t idx; /* Hash Rx queue index. */
MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */
};
+struct mlx5_rxq_priv;
+
/* HW objects operations structure. */
struct mlx5_obj_ops {
- int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on);
- int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx);
+ int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on);
+ int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq);
int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj);
- int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type);
- void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
+ int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type);
+ void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq);
int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
struct mlx5_ind_table_obj *ind_tbl);
int (*ind_table_modify)(struct rte_eth_dev *dev,
#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
-/* MR operations structure. */
-struct mlx5_mr_ops {
- mlx5_reg_mr_t reg_mr;
- mlx5_dereg_mr_t dereg_mr;
-};
-
struct mlx5_priv {
struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
unsigned int mtr_en:1; /* Whether support meter. */
unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
unsigned int lb_used:1; /* Loopback queue is referred to. */
+ uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */
uint16_t domain_id; /* Switch domain identifier. */
uint16_t vport_id; /* Associated VF vport index (if any). */
uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
/* RX/TX queues. */
unsigned int rxqs_n; /* RX queues array size. */
unsigned int txqs_n; /* TX queues array size. */
- struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
+ struct mlx5_external_rxq *ext_rxqs; /* External RX queues array. */
+ struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */
struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
/* Indirection tables. */
LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
+ /* Standalone indirect tables. */
+ LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls;
/* Pointer to next element. */
rte_rwlock_t ind_tbls_lock;
uint32_t refcnt; /**< Reference counter. */
uint32_t link_speed_capa; /* Link speed capabilities. */
struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
- struct mlx5_dev_config config; /* Device configuration. */
+ struct mlx5_port_config config; /* Port configuration. */
/* Context for Verbs allocator. */
int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
uint32_t rss_shared_actions; /* RSS shared actions. */
struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
+ uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */
+ rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */
+ struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM];
+ /* Flex items have been created on the port. */
+ uint32_t flex_item_map; /* Map of allocated flex item elements. */
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+ /* Item template list. */
+ LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt;
+ /* Action template list. */
+ LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at;
+ struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */
+ uint32_t nb_queue; /* HW steering queue number. */
+ /* HW steering queue polling mechanism job descriptor LIFO. */
+ struct mlx5_hw_q *hw_q;
+ /* HW steering rte flow table list header. */
+ LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl;
+ /* HW steering global drop action. */
+ struct mlx5dr_action *hw_drop[MLX5_HW_ACTION_FLAG_MAX]
+ [MLX5DR_TABLE_TYPE_MAX];
+ /* HW steering global drop action. */
+ struct mlx5dr_action *hw_tag[MLX5_HW_ACTION_FLAG_MAX];
+ struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */
+#endif
};
#define PORT_ID(priv) ((priv)->dev_data->port_id)
DR_DUMP_REC_TYPE_PMD_COUNTER = 4430,
};
+/**
+ * Indicates whether HW objects operations can be created by DevX.
+ *
+ * This function is used for both:
+ * Before creation - deciding whether to create HW objects operations by DevX.
+ * After creation - indicator if HW objects operations were created by DevX.
+ *
+ * @param sh
+ * Pointer to shared device context.
+ *
+ * @return
+ * True if HW objects were created by DevX, False otherwise.
+ */
+static inline bool
+mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh)
+{
+ /*
+ * When advanced DR API is available and DV flow is supported and
+ * DevX is supported, HW objects operations are created by DevX.
+ */
+ return (sh->cdev->config.devx && sh->config.dv_flow_en &&
+ sh->dev_cap.dest_tir);
+}
+
/* mlx5.c */
int mlx5_getenv_int(const char *);
struct rte_eth_udp_tunnel *udp_tunnel);
uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev);
int mlx5_dev_close(struct rte_eth_dev *dev);
-int mlx5_net_remove(struct rte_device *dev);
+int mlx5_net_remove(struct mlx5_common_device *cdev);
bool mlx5_is_hpf(struct rte_eth_dev *dev);
bool mlx5_is_sf_repr(struct rte_eth_dev *dev);
void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
for (port_id = mlx5_eth_find_next(0, dev); \
port_id < RTE_MAX_ETHPORTS; \
port_id = mlx5_eth_find_next(port_id + 1, dev))
-int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
+void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
+ struct mlx5_hca_attr *hca_attr);
struct mlx5_dev_ctx_shared *
mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
- const struct mlx5_dev_config *config);
+ struct mlx5_kvargs_ctrl *mkvlist);
void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
+int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);
void mlx5_free_table_hash_list(struct mlx5_priv *priv);
int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
-void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
- struct mlx5_dev_config *config);
+void mlx5_set_min_inline(struct mlx5_priv *priv);
void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
-int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
- struct mlx5_dev_config *config,
- struct rte_device *dpdk_dev);
-int mlx5_dev_configure(struct rte_eth_dev *dev);
-int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
-int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
-int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
-int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
- struct rte_eth_hairpin_cap *cap);
+int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev,
+ struct mlx5_kvargs_ctrl *mkvlist);
+int mlx5_port_args_config(struct mlx5_priv *priv,
+ struct mlx5_kvargs_ctrl *mkvlist,
+ struct mlx5_port_config *config);
+void mlx5_port_args_set_used(const char *name, uint16_t port_id,
+ struct mlx5_kvargs_ctrl *mkvlist);
bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
+void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev);
int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
(((repr_id) >> 12) & 3)
uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
enum rte_eth_representor_type hpf_type);
-int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver,
- size_t fw_size);
-int mlx5_dev_infos_get(struct rte_eth_dev *dev,
- struct rte_eth_dev_info *info);
+int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
+int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
struct rte_eth_fc_conf *fc_conf);
void mlx5_dev_interrupt_handler(void *arg);
void mlx5_dev_interrupt_handler_devx(void *arg);
+void mlx5_dev_interrupt_handler_nl(void *arg);
int mlx5_set_link_down(struct rte_eth_dev *dev);
int mlx5_set_link_up(struct rte_eth_dev *dev);
int mlx5_is_removed(struct rte_eth_dev *dev);
int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);
int mlx5_os_get_stats_n(struct rte_eth_dev *dev);
void mlx5_os_stats_init(struct rte_eth_dev *dev);
+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev);
/* mlx5_mac.c */
struct rte_flow_item_eth *eth_mask);
int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);
struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
+uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev,
+ uint32_t txq);
void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
uint64_t async_id, int status);
void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
- bool clear, uint64_t *pkts, uint64_t *bytes);
+ bool clear, uint64_t *pkts, uint64_t *bytes, void **action);
int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
FILE *file, struct rte_flow_error *error);
int save_dump_file(const unsigned char *data, uint32_t size,
- uint32_t type, uint32_t id, void *arg, FILE *file);
+ uint32_t type, uint64_t id, void *arg, FILE *file);
int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow,
struct rte_flow_query_count *count, struct rte_flow_error *error);
#ifdef HAVE_IBV_FLOW_DV_SUPPORT
/* mlx5_socket.c */
int mlx5_pmd_socket_init(void);
+void mlx5_pmd_socket_uninit(void);
/* mlx5_flow_meter.c */
void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);
/* mlx5_os.c */
+
struct rte_pci_driver;
-int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
+int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
-int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
- const struct mlx5_dev_config *config,
- struct mlx5_dev_ctx_shared *sh);
-int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
-int mlx5_os_net_probe(struct rte_device *dev);
+int mlx5_os_net_probe(struct mlx5_common_device *cdev,
+ struct mlx5_kvargs_ctrl *mkvlist);
void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
-void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
- mlx5_dereg_mr_t *dereg_mr_cb);
void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
uint32_t index);
int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable);
int mlx5_os_set_nonblock_channel_fd(int fd);
void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev);
+void mlx5_os_net_cleanup(void);
/* mlx5_txpp.c */
struct rte_flow_action_conntrack *profile);
int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
struct mlx5_aso_ct_action *ct);
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
+
+/* mlx5_flow_flex.c */
+struct rte_flow_item_flex_handle *
+flow_dv_item_create(struct rte_eth_dev *dev,
+ const struct rte_flow_item_flex_conf *conf,
+ struct rte_flow_error *error);
+int flow_dv_item_release(struct rte_eth_dev *dev,
+ const struct rte_flow_item_flex_handle *flex_handle,
+ struct rte_flow_error *error);
+int mlx5_flex_item_port_init(struct rte_eth_dev *dev);
+void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev);
+void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher,
+ void *key, const struct rte_flow_item *item,
+ bool is_inner);
+int mlx5_flex_acquire_index(struct rte_eth_dev *dev,
+ struct rte_flow_item_flex_handle *handle,
+ bool acquire);
+int mlx5_flex_release_index(struct rte_eth_dev *dev, int index);
+
+/* Flex parser list callbacks. */
+struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx);
+int mlx5_flex_parser_match_cb(void *list_ctx,
+ struct mlx5_list_entry *iter, void *ctx);
+void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry);
+struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx,
+ struct mlx5_list_entry *entry,
+ void *ctx);
+void mlx5_flex_parser_clone_free_cb(void *tool_ctx,
+ struct mlx5_list_entry *entry);
#endif /* RTE_PMD_MLX5_H_ */
git.droids-corp.org / dpdk.git / blobdiff