#include "mlx5_utils.h"
#include "mlx5_os.h"
#include "mlx5_autoconf.h"
-
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+#include "mlx5_dr.h"
+#endif
#define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
MLX5_IPOOL_TAG, /* Pool for tag resource. */
MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
- MLX5_IPOOL_JUMP, /* Pool for jump resource. */
+ MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */
+ /* Pool for HWS group. Jump action will be created internally. */
+ MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP,
MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */
};
+/* The HWS action type root/non-root. */
+enum mlx5_hw_action_flag_type {
+ MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */
+ MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */
+ MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */
+};
+
/* Hlist and list callback context. */
struct mlx5_flow_cb_ctx {
struct rte_eth_dev *dev;
int tx_skew; /* Tx scheduling skew between WQE and data on wire. */
uint32_t reclaim_mode:2; /* Memory reclaim mode. */
uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */
- uint32_t dv_flow_en:1; /* Enable DV flow. */
+ /* Enable DV flow. 1 means SW steering, 2 means HW steering. */
+ unsigned int dv_flow_en:2;
uint32_t dv_xmeta_en:2; /* Enable extensive flow metadata. */
uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */
uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
uint16_t refcnt; /* Reference count for representors. */
};
+/* HW steering queue job descriptor type. */
+enum {
+ MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */
+ MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */
+};
+
+/* HW steering flow management job descriptor. */
+struct mlx5_hw_q_job {
+ uint32_t type; /* Job type. */
+ struct rte_flow_hw *flow; /* Flow attached to the job. */
+ void *user_data; /* Job user data. */
+ uint8_t *encap_data; /* Encap data. */
+};
+
+/* HW steering job descriptor LIFO pool. */
+struct mlx5_hw_q {
+ uint32_t job_idx; /* Free job index. */
+ uint32_t size; /* LIFO size. */
+ struct mlx5_hw_q_job **job; /* LIFO header. */
+} __rte_cache_aligned;
+
#define MLX5_COUNTERS_PER_POOL 512
#define MLX5_MAX_PENDING_QUERIES 4
#define MLX5_CNT_CONTAINER_RESIZE 64
#define MLX5_CNT_ARRAY_IDX(pool, cnt) \
((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
MLX5_CNT_LEN(pool)))
+#define MLX5_TS_MASK_SECS 8ull
+/* timestamp wrapping in seconds, must be power of 2. */
+
/*
* The pool index and offset of counter in the pool array makes up the
* counter index. In case the counter is from pool 0 and offset 0, it
struct mlx5_dev_shared_port {
uint32_t ih_port_id;
uint32_t devx_ih_port_id;
+ uint32_t nl_ih_port_id;
/*
* Interrupt handler port_id. Used by shared interrupt
* handler to find the corresponding rte_eth device
/* If yellow color policy is skipped. */
uint32_t skip_g:1;
/* If green color policy is skipped. */
+ uint32_t mark:1;
+ /* If policy contains mark action. */
rte_spinlock_t sl;
uint32_t ref_cnt;
/* Use count. */
/* Table structure. */
struct mlx5_flow_tbl_resource {
void *obj; /**< Pointer to DR table object. */
- uint32_t refcnt; /**< Reference counter. */
};
#define MLX5_MAX_TABLES UINT16_MAX
uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+ uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */
uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
uint32_t dr_drop_action_en:1; /* Use DR drop action. */
uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */
rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
/* UAR same-page access control required in 32bit implementations. */
#endif
- struct mlx5_hlist *flow_tbls;
+ union {
+ struct mlx5_hlist *flow_tbls; /* SWS flow table. */
+ struct mlx5_hlist *groups; /* HWS flow group. */
+ };
struct mlx5_flow_tunnel_hub *tunnel_hub;
/* Direct Rules tables for FDB, NIC TX+RX */
void *dr_drop_action; /* Pointer to DR drop action, any domain. */
/* Shared interrupt handler section. */
struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */
struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */
+ struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */
void *devx_comp; /* DEVX async comp obj. */
struct mlx5_devx_obj *tis[16]; /* TIS object. */
struct mlx5_devx_obj *td; /* Transport domain. */
uint64_t hash_fields; /* Verbs Hash fields. */
uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
uint32_t key_len; /**< RSS hash key len. */
+ uint32_t hws_flags; /**< HW steering action. */
uint32_t tunnel; /**< Queue in tunnel. */
uint32_t shared_rss; /**< Shared RSS index. */
struct mlx5_ind_table_obj *ind_tbl;
#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
void *action; /* DV QP action pointer. */
#endif
+ uint32_t hws_flags; /* Hw steering flags. */
uint64_t hash_fields; /* Verbs Hash fields. */
uint32_t rss_key_len; /* Hash key length in bytes. */
uint32_t idx; /* Hash Rx queue index. */
/* RX/TX queues. */
unsigned int rxqs_n; /* RX queues array size. */
unsigned int txqs_n; /* TX queues array size. */
+ struct mlx5_external_rxq *ext_rxqs; /* External RX queues array. */
struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */
struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
/* Indirection tables. */
LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
+ /* Standalone indirect tables. */
+ LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls;
/* Pointer to next element. */
rte_rwlock_t ind_tbls_lock;
uint32_t refcnt; /**< Reference counter. */
struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM];
/* Flex items have been created on the port. */
uint32_t flex_item_map; /* Map of allocated flex item elements. */
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+ /* Item template list. */
+ LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt;
+ /* Action template list. */
+ LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at;
+ struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */
+ uint32_t nb_queue; /* HW steering queue number. */
+ /* HW steering queue polling mechanism job descriptor LIFO. */
+ struct mlx5_hw_q *hw_q;
+ /* HW steering rte flow table list header. */
+ LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl;
+ /* HW steering global drop action. */
+ struct mlx5dr_action *hw_drop[MLX5_HW_ACTION_FLAG_MAX]
+ [MLX5DR_TABLE_TYPE_MAX];
+ /* HW steering global drop action. */
+ struct mlx5dr_action *hw_tag[MLX5_HW_ACTION_FLAG_MAX];
+ struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */
+#endif
};
#define PORT_ID(priv) ((priv)->dev_data->port_id)
void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
struct mlx5_hca_attr *hca_attr);
struct mlx5_dev_ctx_shared *
-mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn);
+mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
+ struct mlx5_kvargs_ctrl *mkvlist);
void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);
void mlx5_free_table_hash_list(struct mlx5_priv *priv);
int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
void mlx5_set_min_inline(struct mlx5_priv *priv);
void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
-int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev);
-int mlx5_port_args_config(struct mlx5_priv *priv, struct rte_devargs *devargs,
+int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev,
+ struct mlx5_kvargs_ctrl *mkvlist);
+int mlx5_port_args_config(struct mlx5_priv *priv,
+ struct mlx5_kvargs_ctrl *mkvlist,
struct mlx5_port_config *config);
+void mlx5_port_args_set_used(const char *name, uint16_t port_id,
+ struct mlx5_kvargs_ctrl *mkvlist);
bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);
int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev);
struct rte_eth_fc_conf *fc_conf);
void mlx5_dev_interrupt_handler(void *arg);
void mlx5_dev_interrupt_handler_devx(void *arg);
+void mlx5_dev_interrupt_handler_nl(void *arg);
int mlx5_set_link_down(struct rte_eth_dev *dev);
int mlx5_set_link_up(struct rte_eth_dev *dev);
int mlx5_is_removed(struct rte_eth_dev *dev);
uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
- bool clear, uint64_t *pkts, uint64_t *bytes);
+ bool clear, uint64_t *pkts, uint64_t *bytes, void **action);
int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
FILE *file, struct rte_flow_error *error);
int save_dump_file(const unsigned char *data, uint32_t size,
struct rte_pci_driver;
int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_free_shared_dr(struct mlx5_priv *priv);
-int mlx5_os_net_probe(struct mlx5_common_device *cdev);
+int mlx5_os_net_probe(struct mlx5_common_device *cdev,
+ struct mlx5_kvargs_ctrl *mkvlist);
void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
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