#define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
enum mlx5_ipool_index {
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
MLX5_IPOOL_TAG, /* Pool for tag resource. */
MLX5_IPOOL_JUMP, /* Pool for jump resource. */
MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */
MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */
+ MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */
+ MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
#endif
MLX5_IPOOL_MTR, /* Pool for meter resource. */
MLX5_IPOOL_MCP, /* Pool for metadata resource. */
MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */
- MLX5_IPOOL_TUNNEL_ID, /* Pool for flow tunnel ID. */
- MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */
MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */
MLX5_IPOOL_MAX,
};
int max_sge;
int max_cq;
int max_qp;
+ int max_cqe;
+ uint32_t max_pd;
+ uint32_t max_mr;
+ uint32_t max_srq;
+ uint32_t max_srq_wr;
uint32_t raw_packet_caps;
uint32_t max_rwq_indirection_table_size;
uint32_t max_tso;
extern struct mlx5_shared_data *mlx5_shared_data;
/* Dev ops structs */
-extern const struct eth_dev_ops mlx5_os_dev_ops;
-extern const struct eth_dev_ops mlx5_os_dev_sec_ops;
-extern const struct eth_dev_ops mlx5_os_dev_ops_isolate;
+extern const struct eth_dev_ops mlx5_dev_ops;
+extern const struct eth_dev_ops mlx5_dev_sec_ops;
+extern const struct eth_dev_ops mlx5_dev_ops_isolate;
struct mlx5_counter_ctrl {
/* Name of the counter. */
};
-/**
- * Type of object being allocated.
- */
-enum mlx5_verbs_alloc_type {
- MLX5_VERBS_ALLOC_TYPE_NONE,
- MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
- MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
-};
-
/* Structure for VF VLAN workaround. */
struct mlx5_vf_vlan {
uint32_t tag:12;
uint32_t created:1;
};
-/**
- * Verbs allocator needs a context to know in the callback which kind of
- * resources it is allocating.
- */
-struct mlx5_verbs_alloc_ctx {
- enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
- const void *obj; /* Pointer to the DPDK object. */
-};
-
/* Flow drop context necessary due to Verbs API. */
struct mlx5_drop {
struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
struct mlx5_dev_ctx_shared {
LIST_ENTRY(mlx5_dev_ctx_shared) next;
uint32_t refcnt;
+ uint16_t bond_dev; /* Bond primary device id. */
uint32_t devx:1; /* Opened with DV. */
uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
uint32_t eqn; /* Event Queue number. */
void *pd; /* Protection Domain. */
uint32_t pdn; /* Protection Domain number. */
uint32_t tdn; /* Transport Domain number. */
- char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */
- char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */
+ char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */
+ char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */
struct mlx5_dev_attr device_attr; /* Device properties. */
int numa_node; /* Numa node of backing physical device. */
LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
uint32_t key_len; /**< RSS hash key len. */
uint32_t tunnel; /**< Queue in tunnel. */
uint32_t shared_rss; /**< Shared RSS index. */
+ struct mlx5_ind_table_obj *ind_tbl;
+ /**< Indirection table for shared RSS hash RX queues. */
union {
uint16_t *queue; /**< Destination queues. */
const uint16_t *const_q; /**< Const pointer convert. */
struct mlx5_devx_obj *rqt; /* DevX RQT object. */
};
uint32_t queues_n; /**< Number of queues in the list. */
- uint16_t queues[]; /**< Queue list. */
+ uint16_t *queues; /**< Queue list. */
};
/* Hash Rx queue. */
void *qp; /* Verbs queue pair. */
struct mlx5_devx_obj *tir; /* DevX TIR object. */
};
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
void *action; /* DV QP action pointer. */
#endif
uint64_t hash_fields; /* Verbs Hash fields. */
void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj);
int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n,
struct mlx5_ind_table_obj *ind_tbl);
+ int (*ind_table_modify)(struct rte_eth_dev *dev,
+ const unsigned int log_n,
+ const uint16_t *queues, const uint32_t queues_n,
+ struct mlx5_ind_table_obj *ind_tbl);
void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl);
int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
int tunnel __rte_unused);
#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
+/* MR operations structure. */
+struct mlx5_mr_ops {
+ mlx5_reg_mr_t reg_mr;
+ mlx5_dereg_mr_t dereg_mr;
+};
+
struct mlx5_priv {
struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
unsigned int if_index; /* Associated kernel network device index. */
uint32_t bond_ifindex; /**< Bond interface index. */
- char bond_name[IF_NAMESIZE]; /**< Bond interface name. */
+ char bond_name[MLX5_NAMESIZE]; /**< Bond interface name. */
/* RX/TX queues. */
unsigned int rxqs_n; /* RX queues array size. */
unsigned int txqs_n; /* TX queues array size. */
struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
struct mlx5_dev_config config; /* Device configuration. */
- struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
/* Context for Verbs allocator. */
int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
/* mlx5_ethdev_os.c */
+int mlx5_get_ifname(const struct rte_eth_dev *dev,
+ char (*ifname)[MLX5_NAMESIZE]);
unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
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