net/mlx5: support modify field flow action

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index e61154b..5196a9e 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -15,7 +15,7 @@
 
 #include <rte_pci.h>
 #include <rte_ether.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
 #include <rte_rwlock.h>
 #include <rte_interrupts.h>
 #include <rte_errno.h>
@@ -487,13 +487,7 @@ struct mlx5_aso_sq_elem {
 struct mlx5_aso_sq {
        uint16_t log_desc_n;
        struct mlx5_aso_cq cq;
-       struct mlx5_devx_obj *sq;
-       struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */
-       union {
-               volatile void *umem_buf;
-               volatile struct mlx5_aso_wqe *wqes;
-       };
-       volatile uint32_t *db_rec;
+       struct mlx5_devx_sq sq_obj;
        volatile uint64_t *uar_addr;
        struct mlx5_aso_devx_mr mr;
        uint16_t pi;
@@ -534,6 +528,16 @@ struct mlx5_aso_age_mng {
        struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
 };
 
+/* Management structure for geneve tlv option */
+struct mlx5_geneve_tlv_option_resource {
+       struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */
+       rte_be16_t option_class; /* geneve tlv opt class.*/
+       uint8_t option_type; /* geneve tlv opt type.*/
+       uint8_t length; /* geneve tlv opt length. */
+       uint32_t refcnt; /* geneve tlv object reference counter */
+};
+
+
 #define MLX5_AGE_EVENT_NEW             1
 #define MLX5_AGE_TRIGGER               2
 #define MLX5_AGE_SET(age_info, BIT) \
@@ -615,15 +619,9 @@ struct mlx5_txpp_wq {
        uint32_t cq_ci:24;
        uint32_t arm_sn:2;
        /* Send Queue related data.*/
-       struct mlx5_devx_obj *sq;
-       void *sq_umem;
-       union {
-               volatile void *sq_buf;
-               volatile struct mlx5_wqe *wqes;
-       };
+       struct mlx5_devx_sq sq_obj;
        uint16_t sq_size; /* Number of WQEs in the queue. */
        uint16_t sq_ci; /* Next WQE to execute. */
-       volatile uint32_t *sq_dbrec;
 };
 
 /* Tx packet pacing internal timestamp. */
@@ -683,7 +681,6 @@ struct mlx5_dev_ctx_shared {
        uint16_t bond_dev; /* Bond primary device id. */
        uint32_t devx:1; /* Opened with DV. */
        uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
-       uint32_t eqn; /* Event Queue number. */
        uint32_t max_port; /* Maximal IB device port index. */
        void *ctx; /* Verbs/DV/DevX context. */
        void *pd; /* Protection Domain. */
@@ -740,10 +737,16 @@ struct mlx5_dev_ctx_shared {
        void *devx_rx_uar; /* DevX UAR for Rx. */
        struct mlx5_aso_age_mng *aso_age_mng;
        /* Management data for aging mechanism using ASO Flow Hit. */
+       struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource;
+       /* Management structure for geneve tlv option */
+       rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
        struct mlx5_dev_shared_port port[]; /* per device port data array. */
 };
 
-/* Per-process private structure. */
+/*
+ * Per-process private structure.
+ * Caution, secondary process may rebuild the struct during port start.
+ */
 struct mlx5_proc_priv {
        size_t uar_table_sz;
        /* Size of UAR register table. */
@@ -789,9 +792,10 @@ struct mlx5_rxq_obj {
                        void *ibv_cq; /* Completion Queue. */
                        void *ibv_channel;
                };
+               struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */
                struct {
-                       struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */
-                       struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */
+                       struct mlx5_devx_rq rq_obj; /* DevX RQ object. */
+                       struct mlx5_devx_cq cq_obj; /* DevX CQ object. */
                        void *devx_channel;
                };
        };
@@ -848,11 +852,9 @@ struct mlx5_txq_obj {
                struct {
                        struct rte_eth_dev *dev;
                        struct mlx5_devx_cq cq_obj;
-                       struct mlx5_devx_obj *sq_devx;
-                       void *sq_umem;
-                       void *sq_buf;
-                       int64_t sq_dbrec_offset;
-                       struct mlx5_devx_dbr_page *sq_dbrec_page;
+                       /* DevX CQ object and its resources. */
+                       struct mlx5_devx_sq sq_obj;
+                       /* DevX SQ object and its resources. */
                };
        };
 };
@@ -969,7 +971,6 @@ struct mlx5_priv {
        /* Context for Verbs allocator. */
        int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
        int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
-       struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
        struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
        struct mlx5_hlist *mreg_cp_tbl;
        /* Hash table of Rx metadata register copy table. */
@@ -1000,6 +1001,7 @@ struct rte_hairpin_peer_info {
 
 int mlx5_getenv_int(const char *);
 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
+void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
                              struct rte_eth_udp_tunnel *udp_tunnel);
 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);