#define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
+/*
+ * Number of modification commands.
+ * The maximal actions amount in FW is some constant, and it is 16 in the
+ * latest releases. In some old releases, it will be limited to 8.
+ * Since there is no interface to query the capacity, the maximal value should
+ * be used to allow PMD to create the flow. The validation will be done in the
+ * lower driver layer or FW. A failure will be returned if exceeds the maximal
+ * supported actions number on the root table.
+ * On non-root tables, there is no limitation, but 32 is enough right now.
+ */
+#define MLX5_MAX_MODIFY_NUM 32
+#define MLX5_ROOT_TBL_MODIFY_NUM 16
+
enum mlx5_ipool_index {
#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
};
-/* Hash and cache list callback context. */
+/* The type of flow. */
+enum mlx5_flow_type {
+ MLX5_FLOW_TYPE_CTL, /* Control flow. */
+ MLX5_FLOW_TYPE_GEN, /* General flow. */
+ MLX5_FLOW_TYPE_MCP, /* MCP flow. */
+ MLX5_FLOW_TYPE_MAXI,
+};
+
+/* Hlist and list callback context. */
struct mlx5_flow_cb_ctx {
struct rte_eth_dev *dev;
struct rte_flow_error *error;
void *data;
+ void *data2;
};
/* Device attributes used in mlx5 PMD */
uint32_t max_port; /**< Device maximal port index. */
uint32_t phys_port; /**< Device physical port index. */
int pf_bond; /**< bonding device PF index. < 0 - no bonding */
+ int numa_node; /**< Device numa node. */
struct mlx5_switch_info info; /**< Switch information. */
void *phys_dev; /**< Associated physical device. */
struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
/** Key string for IPC. */
#define MLX5_MP_NAME "net_mlx5_mp"
+/** Initialize a multi-process ID. */
+static inline void
+mlx5_mp_id_init(struct mlx5_mp_id *mp_id, uint16_t port_id)
+{
+ mp_id->port_id = port_id;
+ strlcpy(mp_id->name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
+}
LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
unsigned int hw_padding:1; /* End alignment padding is supported. */
unsigned int vf:1; /* This is a VF. */
- unsigned int tunnel_en:1;
+ unsigned int sf:1; /* This is a SF. */
+ unsigned int tunnel_en:3;
/* Whether tunnel stateless offloads are supported. */
unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
unsigned int cqe_comp:1; /* CQE compression is enabled. */
unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
unsigned int lacp_by_user:1;
/* Enable user to manage LACP traffic. */
- unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
+ unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
unsigned int devx:1; /* Whether devx interface is available or not. */
unsigned int dest_tir:1; /* Whether advanced DR API is available. */
unsigned int reclaim_mode:2; /* Memory reclaim mode. */
unsigned int sys_mem_en:1; /* The default memory allocator. */
unsigned int decap_en:1; /* Whether decap will be used or not. */
unsigned int dv_miss_info:1; /* restore packet after partial hw miss */
+ unsigned int allow_duplicate_pattern:1;
+ /* Allow/Prevent the duplicate rules pattern. */
+ unsigned int mr_mempool_reg_en:1;
+ /* Allow/prevent implicit mempool memory registration. */
struct {
unsigned int enabled:1; /* Whether MPRQ is enabled. */
unsigned int stride_num_n; /* Number of strides. */
struct mlx5_rxq_obj *rxq; /* Rx queue object. */
};
+/* Loopback dummy queue resources required due to Verbs API. */
+struct mlx5_lb_ctx {
+ struct ibv_qp *qp; /* QP object. */
+ void *ibv_cq; /* Completion queue. */
+ uint16_t refcnt; /* Reference count for representors. */
+};
+
#define MLX5_COUNTERS_PER_POOL 512
#define MLX5_MAX_PENDING_QUERIES 4
#define MLX5_CNT_CONTAINER_RESIZE 64
#define MLX5_CNT_SHARED_OFFSET 0x80000000
-#define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET))
#define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \
MLX5_CNT_BATCH_OFFSET)
#define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter))
/* Shared counters information for counters. */
struct mlx5_flow_counter_shared {
- uint32_t id; /**< User counter ID. */
-};
-
-/* Shared counter configuration. */
-struct mlx5_shared_counter_conf {
- struct rte_eth_dev *dev; /* The device shared counter belongs to. */
- uint32_t id; /* The shared counter ID. */
+ union {
+ uint32_t refcnt; /* Only for shared action management. */
+ uint32_t id; /* User counter ID for legacy sharing. */
+ };
};
struct mlx5_flow_counter_pool;
uint64_t errors;
};
-struct mlx5_aso_devx_mr {
- void *buf;
- uint64_t length;
- struct mlx5dv_devx_umem *umem;
- struct mlx5_devx_obj *mkey;
- bool is_indirect;
-};
-
struct mlx5_aso_sq_elem {
union {
struct {
uint16_t burst_size;
};
struct mlx5_aso_mtr *mtr;
+ struct {
+ struct mlx5_aso_ct_action *ct;
+ char *query_data;
+ };
};
};
struct mlx5_aso_cq cq;
struct mlx5_devx_sq sq_obj;
volatile uint64_t *uar_addr;
- struct mlx5_aso_devx_mr mr;
+ struct mlx5_pmd_mr mr;
uint16_t pi;
uint32_t head;
uint32_t tail;
#define MLX5_AGE_TRIGGER 2
#define MLX5_AGE_SET(age_info, BIT) \
((age_info)->flags |= (1 << (BIT)))
+#define MLX5_AGE_UNSET(age_info, BIT) \
+ ((age_info)->flags &= ~(1 << (BIT)))
#define MLX5_AGE_GET(age_info, BIT) \
((age_info)->flags & (1 << (BIT)))
#define GET_PORT_AGE_INFO(priv) \
*/
#define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
-/*ASO flow meter structures*/
+/* ASO flow meter structures */
/* Modify this value if enum rte_mtr_color changes. */
#define RTE_MTR_DROPPED RTE_COLORS
-/* Yellow is not supported. */
-#define MLX5_MTR_RTE_COLORS (RTE_COLOR_GREEN + 1)
+/* Yellow is now supported. */
+#define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1)
/* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */
#define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF
#define MLX5_INVALID_POLICY_ID UINT32_MAX
#define MLX5_MTR_TABLE_ID_SUFFIX 1
/* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */
#define MLX5_MTR_TABLE_ID_DROP 2
+/* Priority of the meter policy matcher. */
+#define MLX5_MTR_POLICY_MATCHER_PRIO 0
+/* Default policy. */
+#define MLX5_MTR_POLICY_MODE_DEF 1
+/* Only green color valid. */
+#define MLX5_MTR_POLICY_MODE_OG 2
+/* Only yellow color valid. */
+#define MLX5_MTR_POLICY_MODE_OY 3
enum mlx5_meter_domain {
MLX5_MTR_DOMAIN_INGRESS,
MLX5_MTR_DOMAIN_EGRESS_BIT | \
MLX5_MTR_DOMAIN_TRANSFER_BIT)
+/* The color tag rule structure. */
+struct mlx5_sub_policy_color_rule {
+ void *rule;
+ /* The color rule. */
+ struct mlx5_flow_dv_matcher *matcher;
+ /* The color matcher. */
+ TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port;
+ /**< Pointer to the next color rule structure. */
+ int32_t src_port;
+ /* On which src port this rule applied. */
+};
+
+TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule);
+
/*
* Meter sub-policy structure.
* Each RSS TIR in meter policy need its own sub-policy resource.
/* Index to TIR resource. */
struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS];
/* Meter jump/drop table. */
- struct mlx5_flow_dv_matcher *color_matcher[RTE_COLORS];
- /* Matcher for Color. */
- void *color_rule[RTE_COLORS];
- /* Meter green/yellow/drop rule. */
+ struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS];
+ /* List for the color rules. */
};
struct mlx5_meter_policy_acts {
/* Index to port ID action resource. */
void *dr_jump_action[MLX5_MTR_DOMAIN_MAX];
/* Jump/drop action per color. */
+ uint16_t queue;
+ /* Queue action configuration. */
+ struct {
+ uint32_t next_mtr_id;
+ /* The next meter id. */
+ void *next_sub_policy;
+ /* Next meter's sub-policy. */
+ };
};
};
/* Flow meter policy parameter structure. */
struct mlx5_flow_meter_policy {
+ struct rte_eth_dev *dev;
+ /* The port dev on which policy is created. */
uint32_t is_rss:1;
/* Is RSS policy table. */
uint32_t ingress:1;
/* Rule applies to egress domain. */
uint32_t transfer:1;
/* Rule applies to transfer domain. */
+ uint32_t is_queue:1;
+ /* Is queue action in policy table. */
+ uint32_t is_hierarchy:1;
+ /* Is meter action in policy table. */
+ uint32_t skip_y:1;
+ /* If yellow color policy is skipped. */
+ uint32_t skip_g:1;
+ /* If green color policy is skipped. */
rte_spinlock_t sl;
uint32_t ref_cnt;
/* Use count. */
#define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3
#define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7
#define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF
+#define MLX5_MTR_CHAIN_MAX_NUM 8
/* Flow meter default policy parameter structure.
* Policy index 0 is reserved by default policy table.
/**< srtcm_rfc2697 struct. */
};
uint32_t ref_cnt; /**< Use count. */
+ uint32_t g_support:1; /**< If G color will be generated. */
+ uint32_t y_support:1; /**< If Y color will be generated. */
};
/* 2 meters in each ASO cache line */
/* Default policy id. */
uint32_t def_policy_ref_cnt;
/** def_policy meter use count. */
- struct mlx5_l3t_tbl *policy_idx_tbl;
- /* Policy index lookup table. */
struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX];
/* Meter drop table. */
struct mlx5_flow_dv_matcher *
} ports[MLX5_BOND_MAX_PORTS];
};
+/* Number of connection tracking objects per pool: must be a power of 2. */
+#define MLX5_ASO_CT_ACTIONS_PER_POOL 64
+
+/* Generate incremental and unique CT index from pool and offset. */
+#define MLX5_MAKE_CT_IDX(pool, offset) \
+ ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1)
+
+/* ASO Conntrack state. */
+enum mlx5_aso_ct_state {
+ ASO_CONNTRACK_FREE, /* Inactive, in the free list. */
+ ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */
+ ASO_CONNTRACK_READY, /* CQE received w/o error. */
+ ASO_CONNTRACK_QUERY, /* WQE for query sent. */
+ ASO_CONNTRACK_MAX, /* Guard. */
+};
+
+/* Generic ASO connection tracking structure. */
+struct mlx5_aso_ct_action {
+ LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */
+ void *dr_action_orig; /* General action object for original dir. */
+ void *dr_action_rply; /* General action object for reply dir. */
+ uint32_t refcnt; /* Action used count in device flows. */
+ uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */
+ uint16_t peer; /* The only peer port index could also use this CT. */
+ enum mlx5_aso_ct_state state; /* ASO CT state. */
+ bool is_original; /* The direction of the DR action to be used. */
+};
+
+/* CT action object state update. */
+#define MLX5_ASO_CT_UPDATE_STATE(c, s) \
+ __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED)
+
+/* ASO connection tracking software pool definition. */
+struct mlx5_aso_ct_pool {
+ uint16_t index; /* Pool index in pools array. */
+ struct mlx5_devx_obj *devx_obj;
+ /* The first devx object in the bulk, used for freeing (not yet). */
+ struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];
+ /* CT action structures bulk. */
+};
+
+LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);
+
+/* Pools management structure for ASO connection tracking pools. */
+struct mlx5_aso_ct_pools_mng {
+ struct mlx5_aso_ct_pool **pools;
+ uint16_t n; /* Total number of pools. */
+ uint16_t next; /* Number of pools in use, index of next free pool. */
+ rte_spinlock_t ct_sl; /* The ASO CT free list lock. */
+ rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */
+ struct aso_ct_list free_cts; /* Free ASO CT objects list. */
+ struct mlx5_aso_sq aso_sq; /* ASO queue objects. */
+};
+
/*
* Shared Infiniband device context for Master/Representors
* which belong to same IB device with multiple IB ports.
uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
+ uint32_t steering_format_version:4;
+ /* Indicates the device steering logic format. */
uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */
+ uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
+ uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
+ uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
+ uint32_t reclaim_mode:1; /* Reclaim memory. */
uint32_t max_port; /* Maximal IB device port index. */
struct mlx5_bond_info bond; /* Bonding information. */
void *ctx; /* Verbs/DV/DevX context. */
struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
struct mlx5_hlist *modify_cmds;
struct mlx5_hlist *tag_table;
- struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */
- struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */
- struct mlx5_cache_list sample_action_list; /* List of sample actions. */
- struct mlx5_cache_list dest_array_list;
+ struct mlx5_list *port_id_action_list; /* Port ID action list. */
+ struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */
+ struct mlx5_list *sample_action_list; /* List of sample actions. */
+ struct mlx5_list *dest_array_list;
/* List of destination array actions. */
struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
void *default_miss_action; /* Default miss action. */
struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
- /* Memory Pool for mlx5 flow resources. */
- struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
+ struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM];
/* Shared interrupt handler section. */
struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */
struct mlx5_flow_mtr_mng *mtrmng;
/* Meter management structure. */
+ struct mlx5_aso_ct_pools_mng *ct_mng;
+ /* Management data for ASO connection tracking. */
+ struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */
struct mlx5_dev_shared_port port[]; /* per device port data array. */
};
/* Hash Rx queue. */
__extension__
struct mlx5_hrxq {
- struct mlx5_cache_entry entry; /* Cache entry. */
+ struct mlx5_list_entry entry; /* List entry. */
uint32_t standalone:1; /* This object used in shared action. */
struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
RTE_STD_C11
int (*txq_obj_modify)(struct mlx5_txq_obj *obj,
enum mlx5_txq_modify_type type, uint8_t dev_port);
void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj);
+ int (*lb_dummy_queue_create)(struct rte_eth_dev *dev);
+ void (*lb_dummy_queue_release)(struct rte_eth_dev *dev);
};
#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
unsigned int sampler_en:1; /* Whether support sampler. */
unsigned int mtr_en:1; /* Whether support meter. */
unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
+ unsigned int lb_used:1; /* Loopback queue is referred to. */
uint16_t domain_id; /* Switch domain identifier. */
uint16_t vport_id; /* Associated VF vport index (if any). */
uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
uint32_t vport_meta_mask; /* Used for vport index field match mask. */
- int32_t representor_id; /* -1 if not a representor. */
+ uint16_t representor_id; /* UINT16_MAX if not a representor. */
int32_t pf_bond; /* >=0, representor owner PF index in bonding. */
unsigned int if_index; /* Associated kernel network device index. */
/* RX/TX queues. */
unsigned int (*reta_idx)[]; /* RETA index table. */
unsigned int reta_idx_n; /* RETA index size. */
struct mlx5_drop drop_queue; /* Flow drop queues. */
- uint32_t flows; /* RTE Flow rules. */
+ void *root_drop_action; /* Pointer to root drop action. */
+ struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI];
+ /* RTE Flow rules. */
uint32_t ctrl_flows; /* Control flow rules. */
rte_spinlock_t flow_list_lock;
struct mlx5_obj_ops obj_ops; /* HW objects operations. */
LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
- struct mlx5_cache_list hrxqs; /* Hash Rx queues. */
+ struct mlx5_list *hrxqs; /* Hash Rx queues. */
LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
/* Indirection tables. */
LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
/* Pointer to next element. */
+ rte_rwlock_t ind_tbls_lock;
uint32_t refcnt; /**< Reference counter. */
/**< Verbs modify header action object. */
uint8_t ft_type; /**< Flow table type, Rx or Tx. */
uint8_t max_lro_msg_size;
- /* Tags resources cache. */
uint32_t link_speed_capa; /* Link speed capabilities. */
struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
/* Hash table of Rx metadata register copy table. */
uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
uint8_t mtr_color_reg; /* Meter color match REG_C. */
- struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */
+ struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */
+ struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */
struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */
uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
uint16_t manual_bind;
};
+#define BUF_SIZE 1024
+enum dr_dump_rec_type {
+ DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410,
+ DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420,
+ DR_DUMP_REC_TYPE_PMD_COUNTER = 4430,
+};
+
/* mlx5.c */
int mlx5_getenv_int(const char *);
void mlx5_proc_priv_uninit(struct rte_eth_dev *dev);
int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
struct rte_eth_udp_tunnel *udp_tunnel);
-uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
+uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev);
int mlx5_dev_close(struct rte_eth_dev *dev);
+int mlx5_net_remove(struct rte_device *dev);
bool mlx5_is_hpf(struct rte_eth_dev *dev);
+bool mlx5_is_sf_repr(struct rte_eth_dev *dev);
void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
/* Macro to iterate over all valid ports for mlx5 driver. */
-#define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
- for (port_id = mlx5_eth_find_next(0, pci_dev); \
+#define MLX5_ETH_FOREACH_DEV(port_id, dev) \
+ for (port_id = mlx5_eth_find_next(0, dev); \
port_id < RTE_MAX_ETHPORTS; \
- port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
+ port_id = mlx5_eth_find_next(port_id + 1, dev))
int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
struct mlx5_dev_ctx_shared *
mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
const struct mlx5_dev_config *config);
void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh);
+int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev);
void mlx5_free_table_hash_list(struct mlx5_priv *priv);
int mlx5_alloc_table_hash_list(struct mlx5_priv *priv);
void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
struct mlx5_dev_config *config);
void mlx5_set_metadata_mask(struct rte_eth_dev *dev);
int mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
- struct mlx5_dev_config *config);
+ struct mlx5_dev_config *config,
+ struct rte_device *dpdk_dev);
int mlx5_dev_configure(struct rte_eth_dev *dev);
int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);
int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);
int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);
+int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);
/* mlx5_ethdev.c */
struct rte_flow_error *error);
int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
struct rte_flow_error *error);
-void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
+void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type,
+ bool active);
int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
const struct rte_flow_action *action, void *data,
bool clear, uint64_t *pkts, uint64_t *bytes);
int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow,
FILE *file, struct rte_flow_error *error);
+int save_dump_file(const unsigned char *data, uint32_t size,
+ uint32_t type, uint32_t id, void *arg, FILE *file);
+int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow,
+ struct rte_flow_query_count *count, struct rte_flow_error *error);
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow,
+ FILE *file, struct rte_flow_error *error);
+#endif
void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
uint32_t nb_contexts, struct rte_flow_error *error);
+int mlx5_validate_action_ct(struct rte_eth_dev *dev,
+ const struct rte_flow_action_conntrack *conntrack,
+ struct rte_flow_error *error);
+
/* mlx5_mp_os.c */
(struct rte_eth_dev *dev,
uint32_t policy_id,
uint32_t *policy_idx);
+struct mlx5_flow_meter_policy *
+mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev,
+ struct mlx5_flow_meter_policy *policy);
int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
struct rte_mtr_error *error);
+void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev);
/* mlx5_os.c */
struct rte_pci_driver;
const struct mlx5_dev_config *config,
struct mlx5_dev_ctx_shared *sh);
int mlx5_os_get_pdn(void *pd, uint32_t *pdn);
-int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
- struct rte_pci_device *pci_dev);
+int mlx5_os_net_probe(struct rte_device *dev);
void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh);
void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
struct mlx5_aso_mtr *mtr);
int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
struct mlx5_aso_mtr *mtr);
+int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
+ struct mlx5_aso_ct_action *ct,
+ const struct rte_flow_action_conntrack *profile);
+int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
+ struct mlx5_aso_ct_action *ct);
+int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
+ struct mlx5_aso_ct_action *ct,
+ struct rte_flow_action_conntrack *profile);
+int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
+ struct mlx5_aso_ct_action *ct);
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
#endif /* RTE_PMD_MLX5_H_ */
git.droids-corp.org / dpdk.git / blobdiff