net/mlx5: adjust maximum LRO message size

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 422a70f..6cb8858 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -36,6 +36,7 @@
 #include "mlx5_mr.h"
 #include "mlx5_autoconf.h"
 #include "mlx5_defs.h"
+#include "mlx5_glue.h"
 
 enum {
        PCI_VENDOR_ID_MELLANOX = 0x15b3,
@@ -344,6 +345,13 @@ struct mlx5_devx_tir_attr {
        struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
 };
 
+/* RQT attributes structure, used by RQT operations. */
+struct mlx5_devx_rqt_attr {
+       uint32_t rqt_max_size:16;
+       uint32_t rqt_actual_size:16;
+       uint32_t rq_list[];
+};
+
 /**
  * Type of object being allocated.
  */
@@ -367,7 +375,7 @@ LIST_HEAD(mlx5_mr_list, mlx5_mr);
 /* Flow drop context necessary due to Verbs API. */
 struct mlx5_drop {
        struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
-       struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
+       struct mlx5_rxq_obj *rxq; /* Rx queue object. */
 };
 
 #define MLX5_COUNTERS_PER_POOL 512
@@ -491,6 +499,21 @@ struct mlx5_flow_tbl_resource {
 #define MLX5_MAX_TABLES_FDB 32
 #define MLX5_GROUP_FACTOR 1
 
+#define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
+#define MLX5_DBR_SIZE 8
+#define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
+#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
+
+struct mlx5_devx_dbr_page {
+       /* Door-bell records, must be first member in structure. */
+       uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
+       LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
+       struct mlx5dv_devx_umem *umem;
+       uint32_t dbr_count; /* Number of door-bell records in use. */
+       /* 1 bit marks matching door-bell is in use. */
+       uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
+};
+
 /*
  * Shared Infiniband device context for Master/Representors
  * which belong to same IB device with multiple IB ports.
@@ -502,6 +525,7 @@ struct mlx5_ibv_shared {
        uint32_t max_port; /* Maximal IB device port index. */
        struct ibv_context *ctx; /* Verbs/DV context. */
        struct ibv_pd *pd; /* Protection Domain. */
+       uint32_t pdn; /* Protection Domain number. */
        uint32_t tdn; /* Transport Domain number. */
        char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
        char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
@@ -590,17 +614,18 @@ struct mlx5_priv {
        struct mlx5_flows flows; /* RTE Flow rules. */
        struct mlx5_flows ctrl_flows; /* Control flow rules. */
        LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
-       LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
+       LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
        LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
        LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
        LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
-       /* Verbs Indirection tables. */
-       LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
+       /* Indirection tables. */
+       LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
        /* Pointer to next element. */
        rte_atomic32_t refcnt; /**< Reference counter. */
        struct ibv_flow_action *verbs_action;
        /**< Verbs modify header action object. */
        uint8_t ft_type; /**< Flow table type, Rx or Tx. */
+       uint8_t max_lro_msg_size;
        /* Tags resources cache. */
        uint32_t link_speed_capa; /* Link speed capabilities. */
        struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
@@ -611,6 +636,7 @@ struct mlx5_priv {
        int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
        int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
        uint32_t nl_sn; /* Netlink message sequence number. */
+       LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
 #ifndef RTE_ARCH_64
        rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
        rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
@@ -625,6 +651,10 @@ struct mlx5_priv {
 
 int mlx5_getenv_int(const char *);
 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
+int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
+                    struct mlx5_devx_dbr_page **dbr_page);
+int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
+                        uint64_t offset);
 
 /* mlx5_ethdev.c */
 
@@ -831,5 +861,7 @@ int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
                            struct mlx5_devx_modify_rq_attr *rq_attr);
 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
                                        struct mlx5_devx_tir_attr *tir_attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
+                                       struct mlx5_devx_rqt_attr *rqt_attr);
 
 #endif /* RTE_PMD_MLX5_H_ */