net/mlx5: introduce Tx burst routine template

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 6230371..7aad94d 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -170,6 +170,11 @@ struct mlx5_hca_attr {
        uint32_t eswitch_manager:1;
        uint32_t flow_counters_dump:1;
        uint8_t flow_counter_bulk_alloc_bitmap;
+       uint32_t eth_net_offloads:1;
+       uint32_t eth_virt:1;
+       uint32_t wqe_vlan_insert:1;
+       uint32_t wqe_inline_mode:2;
+       uint32_t vport_inline_mode:3;
 };
 
 /* Flow list . */
@@ -189,6 +194,7 @@ TAILQ_HEAD(mlx5_flows, rte_flow);
 struct mlx5_dev_config {
        unsigned int hw_csum:1; /* Checksum offload is supported. */
        unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
+       unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
        unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
        unsigned int hw_padding:1; /* End alignment padding is supported. */
        unsigned int vf:1; /* This is a VF. */
@@ -198,9 +204,7 @@ struct mlx5_dev_config {
        unsigned int cqe_comp:1; /* CQE compression is enabled. */
        unsigned int cqe_pad:1; /* CQE padding is enabled. */
        unsigned int tso:1; /* Whether TSO is supported. */
-       unsigned int tx_vec_en:1; /* Tx vector is enabled. */
        unsigned int rx_vec_en:1; /* Rx vector is enabled. */
-       unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
        unsigned int mr_ext_memseg_en:1;
        /* Whether memseg should be extended for MR creation. */
        unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
@@ -224,10 +228,10 @@ struct mlx5_dev_config {
        unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
        unsigned int ind_table_max_size; /* Maximum indirection table size. */
        unsigned int max_dump_files_num; /* Maximum dump files per queue. */
-       int txq_inline; /* Maximum packet size for inlining. */
        int txqs_inline; /* Queue number threshold for inlining. */
-       int txqs_vec; /* Queue number threshold for vectorized Tx. */
-       int inline_max_packet_sz; /* Max packet size for inlining. */
+       int txq_inline_min; /* Minimal amount of data bytes to inline. */
+       int txq_inline_max; /* Max packet size for inlining with SEND. */
+       int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
        struct mlx5_hca_attr hca_attr; /* HCA attributes. */
 };