};
#define MLX5_MAX_TABLES UINT16_MAX
+#define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
+#define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
#define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
/* Reserve the last two tables for metadata register copy. */
#define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
void *fdb_domain; /* FDB Direct Rules name space handle. */
struct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];
/* FDB Direct Rules tables. */
+ struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl;
+ /* FDB meter suffix rules table. */
void *rx_domain; /* RX Direct Rules name space handle. */
struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];
/* RX Direct Rules tables. */
+ struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl;
+ /* RX meter suffix rules table. */
void *tx_domain; /* TX Direct Rules name space handle. */
struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES];
/* TX Direct Rules tables. */
+ struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl;
+ /* TX meter suffix rules table. */
void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
/* TX Direct Rules tables/ */
/* Table of UAR registers for each process. */
};
+/* MTR profile list. */
+TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
+
#define MLX5_PROC_PRIV(port_id) \
((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
struct mlx5_flow_id_pool *qrss_id_pool;
struct mlx5_hlist *mreg_cp_tbl;
/* Hash table of Rx metadata register copy table. */
+ uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
+ uint8_t mtr_color_reg; /* Meter color match REG_C. */
+ struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
#ifndef RTE_ARCH_64
rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];