crypto/mlx5: add WQE set initialization

[dpdk.git] / drivers / net / mlx5 / mlx5.h

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 48ccedc..94618e1 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -36,6 +36,19 @@
 
 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)
 
+/*
+ * Number of modification commands.
+ * The maximal actions amount in FW is some constant, and it is 16 in the
+ * latest releases. In some old releases, it will be limited to 8.
+ * Since there is no interface to query the capacity, the maximal value should
+ * be used to allow PMD to create the flow. The validation will be done in the
+ * lower driver layer or FW. A failure will be returned if exceeds the maximal
+ * supported actions number on the root table.
+ * On non-root tables, there is no limitation, but 32 is enough right now.
+ */
+#define MLX5_MAX_MODIFY_NUM                    32
+#define MLX5_ROOT_TBL_MODIFY_NUM               16
+
 enum mlx5_ipool_index {
 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
        MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
@@ -84,6 +97,7 @@ struct mlx5_flow_cb_ctx {
        struct rte_eth_dev *dev;
        struct rte_flow_error *error;
        void *data;
+       void *data2;
 };
 
 /* Device attributes used in mlx5 PMD */
@@ -1104,6 +1118,7 @@ struct mlx5_dev_ctx_shared {
        uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
        uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
        uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
+       uint32_t reclaim_mode:1; /* Reclaim memory. */
        uint32_t max_port; /* Maximal IB device port index. */
        struct mlx5_bond_info bond; /* Bonding information. */
        void *ctx; /* Verbs/DV/DevX context. */
@@ -1139,14 +1154,15 @@ struct mlx5_dev_ctx_shared {
        struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */
        struct mlx5_hlist *modify_cmds;
        struct mlx5_hlist *tag_table;
-       struct mlx5_list port_id_action_list; /* Port ID action list. */
-       struct mlx5_list push_vlan_action_list; /* Push VLAN actions. */
-       struct mlx5_list sample_action_list; /* List of sample actions. */
-       struct mlx5_list dest_array_list;
+       struct mlx5_list *port_id_action_list; /* Port ID action list. */
+       struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */
+       struct mlx5_list *sample_action_list; /* List of sample actions. */
+       struct mlx5_list *dest_array_list;
        /* List of destination array actions. */
        struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
        void *default_miss_action; /* Default miss action. */
        struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
+       struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM];
        /* Memory Pool for mlx5 flow resources. */
        struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */
        /* Shared interrupt handler section. */
@@ -1384,7 +1400,7 @@ struct mlx5_priv {
        struct mlx5_obj_ops obj_ops; /* HW objects operations. */
        LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
        LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
-       struct mlx5_list hrxqs; /* Hash Rx queues. */
+       struct mlx5_list *hrxqs; /* Hash Rx queues. */
        LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
        LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
        /* Indirection tables. */