#include "mlx5_tx.h"
#include "mlx5_autoconf.h"
#include "mlx5_devx.h"
+#include "rte_pmd_mlx5.h"
/**
* Get the interface index from device name.
rte_errno = EINVAL;
return -rte_errno;
}
- priv->rss_conf.rss_key =
- mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE,
- MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY);
+ priv->rss_conf.rss_key = mlx5_realloc(priv->rss_conf.rss_key,
+ MLX5_MEM_RTE,
+ MLX5_RSS_HASH_KEY_LEN, 0,
+ SOCKET_ID_ANY);
if (!priv->rss_conf.rss_key) {
DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)",
dev->data->port_id, rxqs_n);
MLX5_MEM_RTE | MLX5_MEM_ZERO,
sizeof(void *) * rxqs_n, 0,
SOCKET_ID_ANY);
- if (priv->rxq_privs == NULL) {
+ if (rxqs_n && priv->rxq_privs == NULL) {
DRV_LOG(ERR, "port %u cannot allocate rxq private data",
dev->data->port_id);
rte_errno = ENOMEM;
rte_errno = EINVAL;
return -rte_errno;
}
+ if (priv->ext_rxqs && rxqs_n >= MLX5_EXTERNAL_RX_QUEUE_ID_MIN) {
+ DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u), "
+ "the maximal number of internal Rx queues is %u",
+ dev->data->port_id, rxqs_n,
+ MLX5_EXTERNAL_RX_QUEUE_ID_MIN - 1);
+ rte_errno = EINVAL;
+ return -rte_errno;
+ }
if (rxqs_n != priv->rxqs_n) {
DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
dev->data->port_id, priv->rxqs_n, rxqs_n);
for (i = 0, j = 0; i < rxqs_n; i++) {
struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);
- if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
+ if (rxq_ctrl && !rxq_ctrl->is_hairpin)
rss_queue_arr[j++] = i;
}
rss_queue_n = j;
mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_dev_config *config = &priv->config;
+ struct mlx5_port_config *config = &priv->config;
unsigned int inlen;
uint16_t nb_max;
mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_dev_config *config = &priv->config;
unsigned int max;
/* FIXME: we should ask the device for these values. */
info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;
info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);
info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG;
- info->rx_seg_capa.multi_pools = !config->mprq.enabled;
- info->rx_seg_capa.offset_allowed = !config->mprq.enabled;
+ info->rx_seg_capa.multi_pools = !priv->config.mprq.enabled;
+ info->rx_seg_capa.offset_allowed = !priv->config.mprq.enabled;
info->rx_seg_capa.offset_align_log2 = 0;
info->rx_offload_capa = (mlx5_get_rx_port_offloads() |
info->rx_queue_offload_capa);
{
struct mlx5_priv *priv = dev->data->dev_private;
- if (!priv->sh->cdev->config.devx || !priv->sh->dev_cap.dest_tir ||
- !priv->sh->config.dv_flow_en) {
+ if (!mlx5_devx_obj_ops_en(priv->sh)) {
rte_errno = ENOTSUP;
return -rte_errno;
}