MLX5_ASSERT(priv);
MLX5_ASSERT(priv->if_index);
- ifindex = priv->if_index;
+ ifindex = priv->bond_ifindex > 0 ? priv->bond_ifindex : priv->if_index;
if (!ifindex)
rte_errno = ENXIO;
return ifindex;
if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
-
+ if ((dev->data->dev_conf.txmode.offloads &
+ DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
+ rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) {
+ DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag",
+ dev->data->port_id);
+ return -rte_errno;
+ }
memcpy(priv->rss_conf.rss_key,
use_app_rss_key ?
dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
-mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
- struct rte_eth_hairpin_cap *cap)
+mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
{
struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_dev_config *config = &priv->config;
- if (priv->sh->devx == 0) {
+ if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {
rte_errno = ENOTSUP;
return -rte_errno;
}