net/sfc/base: remove obsolete check for pre-Siena hardware

[dpdk.git] / drivers / net / mlx5 / mlx5_ethdev.c

diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 318bc9d..a3cef68 100644 (file)
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -56,6 +56,7 @@
 
 #include <rte_atomic.h>
 #include <rte_ethdev.h>
+#include <rte_bus_pci.h>
 #include <rte_mbuf.h>
 #include <rte_common.h>
 #include <rte_interrupts.h>
@@ -575,8 +576,29 @@ dev_configure(struct rte_eth_dev *dev)
        unsigned int i;
        unsigned int j;
        unsigned int reta_idx_n;
+       const uint8_t use_app_rss_key =
+               !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len;
 
-       priv->rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
+       if (use_app_rss_key &&
+           (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len !=
+            rss_hash_default_key_len)) {
+               /* MLX5 RSS only support 40bytes key. */
+               return EINVAL;
+       }
+       priv->rss_conf.rss_key =
+               rte_realloc(priv->rss_conf.rss_key,
+                           rss_hash_default_key_len, 0);
+       if (!priv->rss_conf.rss_key) {
+               ERROR("cannot allocate RSS hash key memory (%u)", rxqs_n);
+               return ENOMEM;
+       }
+       memcpy(priv->rss_conf.rss_key,
+              use_app_rss_key ?
+              dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
+              rss_hash_default_key,
+              rss_hash_default_key_len);
+       priv->rss_conf.rss_key_len = rss_hash_default_key_len;
+       priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
        priv->rxqs = (void *)dev->data->rx_queues;
        priv->txqs = (void *)dev->data->tx_queues;
        if (txqs_n != priv->txqs_n) {
@@ -676,7 +698,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
                  DEV_RX_OFFLOAD_UDP_CKSUM |
                  DEV_RX_OFFLOAD_TCP_CKSUM) :
                 0) |
-               (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0);
+               (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) |
+               DEV_RX_OFFLOAD_TIMESTAMP;
+
        if (!priv->mps)
                info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
        if (priv->hw_csum)
@@ -694,9 +718,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
                info->if_index = if_nametoindex(ifname);
        info->reta_size = priv->reta_idx_n ?
                priv->reta_idx_n : priv->ind_table_max_size;
-       info->hash_key_size = ((*priv->rss_conf) ?
-                              (*priv->rss_conf)[0]->rss_key_len :
-                              0);
+       info->hash_key_size = priv->rss_conf.rss_key_len;
        info->speed_capa = priv->link_speed_capa;
        priv_unlock(priv);
 }
@@ -843,39 +865,39 @@ mlx5_link_update_unlocked_gs(struct rte_eth_dev *dev, int wait_to_complete)
        sc = ecmd->link_mode_masks[0] |
                ((uint64_t)ecmd->link_mode_masks[1] << 32);
        priv->link_speed_capa = 0;
-       if (sc & ETHTOOL_LINK_MODE_Autoneg_BIT)
+       if (sc & MLX5_BITSHIFT(ETHTOOL_LINK_MODE_Autoneg_BIT))
                priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
-       if (sc & (ETHTOOL_LINK_MODE_1000baseT_Full_BIT |
-                 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_1000baseT_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_1G;
-       if (sc & (ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT |
-                 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT |
-                 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_10G;
-       if (sc & (ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT |
-                 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_20G;
-       if (sc & (ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_40G;
-       if (sc & (ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_56G;
-       if (sc & (ETHTOOL_LINK_MODE_25000baseCR_Full_BIT |
-                 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT |
-                 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_25G;
-       if (sc & (ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT |
-                 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_50G;
-       if (sc & (ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT |
-                 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT))
+       if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT) |
+                 MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT)))
                priv->link_speed_capa |= ETH_LINK_SPEED_100G;
        dev_link.link_duplex = ((ecmd->duplex == DUPLEX_HALF) ?
                                ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);