}
if ((dev->data->dev_conf.txmode.offloads &
- DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
+ RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) &&
rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) {
DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag",
dev->data->port_id);
info->default_txportconf.ring_size = 256;
info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST;
info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST;
- if ((priv->link_speed_capa & ETH_LINK_SPEED_200G) |
- (priv->link_speed_capa & ETH_LINK_SPEED_100G)) {
+ if ((priv->link_speed_capa & RTE_ETH_LINK_SPEED_200G) |
+ (priv->link_speed_capa & RTE_ETH_LINK_SPEED_100G)) {
info->default_rxportconf.nb_queues = 16;
info->default_txportconf.nb_queues = 16;
if (dev->data->nb_rx_queues > 2 ||
if (priv->representor) {
uint16_t port_id;
- MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
+ MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
struct mlx5_priv *opriv =
rte_eth_devices[port_id].data->dev_private;