net/mlx5: fix indexed pools allocation on Windows

[dpdk.git] / drivers / net / mlx5 / mlx5_flow_aso.c

diff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c
index 92fa9ed..e11327a 100644 (file)
--- a/drivers/net/mlx5/mlx5_flow_aso.c
+++ b/drivers/net/mlx5/mlx5_flow_aso.c
@@ -747,6 +747,27 @@ mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
                wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
                                RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
                                (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
+       switch (fmp->profile.alg) {
+       case RTE_MTR_SRTCM_RFC2697:
+               /* Only needed for RFC2697. */
+               if (fm->profile->srtcm_prm.ebs_eir)
+                       wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm |=
+                                       RTE_BE32(1 << ASO_DSEG_BO_OFFSET);
+               break;
+       case RTE_MTR_TRTCM_RFC2698:
+               wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm |=
+                               RTE_BE32(1 << ASO_DSEG_BBOG_OFFSET);
+               break;
+       case RTE_MTR_TRTCM_RFC4115:
+       default:
+               break;
+       }
+       /*
+        * Note:
+        * Due to software performance reason, the token fields will not be
+        * set when posting the WQE to ASO SQ. It will be filled by the HW
+        * automatically.
+        */
        sq->head++;
        sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
        rte_io_wmb();
@@ -1388,3 +1409,44 @@ data_handle:
                mlx5_aso_ct_obj_analyze(profile, out_data);
        return ret;
 }
+
+/*
+ * Make sure the conntrack context is synchronized with hardware before
+ * creating a flow rule that uses it.
+ *
+ * @param[in] sh
+ *   Pointer to shared device context.
+ * @param[in] ct
+ *   Pointer to connection tracking offload object.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
+                     struct mlx5_aso_ct_action *ct)
+{
+       struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
+       uint32_t poll_cqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
+       enum mlx5_aso_ct_state state =
+                               __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
+
+       if (state == ASO_CONNTRACK_FREE) {
+               rte_errno = ENXIO;
+               return -rte_errno;
+       } else if (state == ASO_CONNTRACK_READY ||
+                  state == ASO_CONNTRACK_QUERY) {
+               return 0;
+       }
+       do {
+               mlx5_aso_ct_completion_handle(mng);
+               state = __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
+               if (state == ASO_CONNTRACK_READY ||
+                   state == ASO_CONNTRACK_QUERY)
+                       return 0;
+               /* Waiting for CQE ready, consider should block or sleep. */
+               rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
+       } while (--poll_cqe_times);
+       rte_errno = EBUSY;
+       return -rte_errno;
+}