if (data->offset < 32) {
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_DMAC_47_16};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
}
info[idx] = (struct field_modify_info){2, 4 * idx,
MLX5_MODI_OUT_DMAC_15_0};
- mask[idx] = (width) ? 0x0000ffff : 0x0;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
if (data->offset < 32) {
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_SMAC_47_16};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
}
info[idx] = (struct field_modify_info){2, 4 * idx,
MLX5_MODI_OUT_SMAC_15_0};
- mask[idx] = (width) ? 0x0000ffff : 0x0;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
case RTE_FLOW_FIELD_VLAN_ID:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_FIRST_VID};
- if (mask) {
- mask[idx] = 0x00000fff;
- if (width < 12)
- mask[idx] = (mask[idx] << (12 - width)) &
- 0x00000fff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x00000fff >>
+ (12 - width));
break;
case RTE_FLOW_FIELD_MAC_TYPE:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_ETHERTYPE};
- if (mask) {
- mask[idx] = 0x0000ffff;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
break;
case RTE_FLOW_FIELD_IPV4_DSCP:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IP_DSCP};
- if (mask) {
- mask[idx] = 0x0000003f;
- if (width < 6)
- mask[idx] = (mask[idx] << (6 - width)) &
- 0x0000003f;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000003f >>
+ (6 - width));
break;
case RTE_FLOW_FIELD_IPV4_TTL:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IPV4_TTL};
- if (mask) {
- mask[idx] = 0x000000ff;
- if (width < 8)
- mask[idx] = (mask[idx] << (8 - width)) &
- 0x000000ff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x000000ff >>
+ (8 - width));
break;
case RTE_FLOW_FIELD_IPV4_SRC:
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_SIPV4};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
break;
case RTE_FLOW_FIELD_IPV4_DST:
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_DIPV4};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
break;
case RTE_FLOW_FIELD_IPV6_DSCP:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IP_DSCP};
- if (mask) {
- mask[idx] = 0x0000003f;
- if (width < 6)
- mask[idx] = (mask[idx] << (6 - width)) &
- 0x0000003f;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000003f >>
+ (6 - width));
break;
case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
info[idx] = (struct field_modify_info){1, 0,
MLX5_MODI_OUT_IPV6_HOPLIMIT};
- if (mask) {
- mask[idx] = 0x000000ff;
- if (width < 8)
- mask[idx] = (mask[idx] << (8 - width)) &
- 0x000000ff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x000000ff >>
+ (8 - width));
break;
case RTE_FLOW_FIELD_IPV6_SRC:
if (mask) {
if (data->offset < 32) {
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_SIPV6_127_96};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
info[idx] = (struct field_modify_info){4,
4 * idx,
MLX5_MODI_OUT_SIPV6_95_64};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
info[idx] = (struct field_modify_info){4,
8 * idx,
MLX5_MODI_OUT_SIPV6_63_32};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
}
info[idx] = (struct field_modify_info){4, 12 * idx,
MLX5_MODI_OUT_SIPV6_31_0};
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
if (data->offset < 32) {
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_DIPV6_127_96};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
info[idx] = (struct field_modify_info){4,
4 * idx,
MLX5_MODI_OUT_DIPV6_95_64};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
info[idx] = (struct field_modify_info){4,
8 * idx,
MLX5_MODI_OUT_DIPV6_63_32};
- mask[idx] = 0xffffffff;
if (width < 32) {
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
width = 0;
} else {
+ mask[idx] = RTE_BE32(0xffffffff);
width -= 32;
}
if (!width)
}
info[idx] = (struct field_modify_info){4, 12 * idx,
MLX5_MODI_OUT_DIPV6_31_0};
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
case RTE_FLOW_FIELD_TCP_PORT_SRC:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_TCP_SPORT};
- if (mask) {
- mask[idx] = 0x0000ffff;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
break;
case RTE_FLOW_FIELD_TCP_PORT_DST:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_TCP_DPORT};
- if (mask) {
- mask[idx] = 0x0000ffff;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
break;
case RTE_FLOW_FIELD_TCP_SEQ_NUM:
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_TCP_SEQ_NUM};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = (mask[idx] << (32 - width));
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
break;
case RTE_FLOW_FIELD_TCP_ACK_NUM:
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_OUT_TCP_ACK_NUM};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = (mask[idx] << (32 - width));
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
break;
case RTE_FLOW_FIELD_TCP_FLAGS:
info[idx] = (struct field_modify_info){1, 0,
- MLX5_MODI_IN_TCP_FLAGS};
- if (mask) {
- mask[idx] = 0x0000003f;
- if (width < 6)
- mask[idx] = (mask[idx] << (6 - width)) &
- 0x0000003f;
- }
+ MLX5_MODI_OUT_TCP_FLAGS};
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000003f >>
+ (6 - width));
break;
case RTE_FLOW_FIELD_UDP_PORT_SRC:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_UDP_SPORT};
- if (mask) {
- mask[idx] = 0x0000ffff;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
break;
case RTE_FLOW_FIELD_UDP_PORT_DST:
info[idx] = (struct field_modify_info){2, 0,
MLX5_MODI_OUT_UDP_DPORT};
- if (mask) {
- mask[idx] = 0x0000ffff;
- if (width < 16)
- mask[idx] = (mask[idx] << (16 - width)) &
- 0x0000ffff;
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+ (16 - width));
break;
case RTE_FLOW_FIELD_VXLAN_VNI:
/* not supported yet */
case RTE_FLOW_FIELD_GTP_TEID:
info[idx] = (struct field_modify_info){4, 0,
MLX5_MODI_GTP_TEID};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
- }
+ if (mask)
+ mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
break;
case RTE_FLOW_FIELD_TAG:
{
MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
info[idx] = (struct field_modify_info){4, 0,
reg_to_field[reg]};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
- }
+ if (mask)
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
}
break;
case RTE_FLOW_FIELD_MARK:
MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
info[idx] = (struct field_modify_info){4, 0,
reg_to_field[reg]};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
- }
+ if (mask)
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
}
break;
case RTE_FLOW_FIELD_META:
MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
info[idx] = (struct field_modify_info){4, 0,
reg_to_field[reg]};
- if (mask) {
- mask[idx] = 0xffffffff;
- if (width < 32)
- mask[idx] = mask[idx] << (32 - width);
- }
+ if (mask)
+ mask[idx] =
+ rte_cpu_to_be_32(0xffffffff >>
+ (32 - width));
}
break;
case RTE_FLOW_FIELD_POINTER:
if (mask[idx]) {
memcpy(&value[idx],
(void *)(uintptr_t)data->value, 32);
- value[idx] = RTE_BE32(value[idx]);
+ value[idx] = rte_cpu_to_be_32(value[idx]);
break;
}
}
case RTE_FLOW_FIELD_VALUE:
for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
if (mask[idx]) {
- value[idx] = RTE_BE32((uint32_t)data->value);
+ value[idx] =
+ rte_cpu_to_be_32((uint32_t)data->value);
break;
}
}
"isn't supported");
if (reg != REG_A)
nic_mask.data = priv->sh->dv_meta_mask;
- } else if (attr->transfer) {
- return rte_flow_error_set(error, ENOTSUP,
+ } else {
+ if (attr->transfer)
+ return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM, item,
"extended metadata feature "
"should be enabled when "
"meta item is requested "
"with e-switch mode ");
+ if (attr->ingress)
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "match on metadata for ingress "
+ "is not supported in legacy "
+ "metadata mode");
}
if (!mask)
mask = &rte_flow_item_meta_mask;
"cannot create action");
return NULL;
}
+ cache->idx = idx;
return &cache->entry;
}
"cannot create push vlan action");
return NULL;
}
+ cache->idx = idx;
return &cache->entry;
}
/**
* Validate the generic modify field actions.
- *
+ * @param[in] dev
+ * Pointer to the rte_eth_dev structure.
* @param[in] action_flags
* Holds the actions detected until now.
* @param[in] action
* Pointer to the modify action.
- * @param[in] item_flags
- * Holds the items detected.
+ * @param[in] attr
+ * Pointer to the flow attributes.
* @param[out] error
* Pointer to error structure.
*
* a negative errno value otherwise and rte_errno is set.
*/
static int
-flow_dv_validate_action_modify_field(const uint64_t action_flags,
+flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
+ const uint64_t action_flags,
const struct rte_flow_action *action,
+ const struct rte_flow_attr *attr,
struct rte_flow_error *error)
{
int ret = 0;
+ struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_dev_config *config = &priv->config;
const struct rte_flow_action_modify_field *action_modify_field =
action->conf;
uint32_t dst_width =
if (ret)
return ret;
+ if (action_modify_field->width == 0)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "no bits are requested to be modified");
+ else if (action_modify_field->width > dst_width ||
+ action_modify_field->width > src_width)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "cannot modify more bits than"
+ " the width of a field");
if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
- if (action_modify_field->dst.offset >= dst_width ||
+ if ((action_modify_field->dst.offset +
+ action_modify_field->width > dst_width) ||
(action_modify_field->dst.offset % 32))
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ACTION,
}
if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
- if (action_modify_field->src.offset >= src_width ||
+ if (!attr->transfer && !attr->group)
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL, "modify field action "
+ "is not supported for group 0");
+ if ((action_modify_field->src.offset +
+ action_modify_field->width > src_width) ||
(action_modify_field->src.offset % 32))
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ACTION,
NULL,
"cannot copy from inner headers");
}
- if (action_modify_field->width == 0)
- return rte_flow_error_set(error, EINVAL,
- RTE_FLOW_ERROR_TYPE_ACTION,
- NULL,
- "width is required for modify action");
if (action_modify_field->dst.field ==
action_modify_field->src.field)
return rte_flow_error_set(error, EINVAL,
NULL,
"modifications of an arbitrary"
" place in a packet is not supported");
+ if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
+ action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "modifications of the 802.1Q Tag"
+ " Identifier is not supported");
+ if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
+ action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "modifications of the VXLAN Network"
+ " Identifier is not supported");
+ if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
+ action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "modifications of the GENEVE Network"
+ " Identifier is not supported");
+ if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
+ action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
+ if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
+ !mlx5_flow_ext_mreg_supported(dev))
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION, action,
+ "cannot modify mark without extended"
+ " metadata register support");
+ }
if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ACTION,
* Pointer to the RSS action in sample action list.
* @param[out] count
* Pointer to the COUNT action in sample action list.
+ * @param[out] fdb_mirror_limit
+ * Pointer to the FDB mirror limitation flag.
* @param[out] error
* Pointer to error structure.
*
const struct rte_flow_action_rss *rss,
const struct rte_flow_action_rss **sample_rss,
const struct rte_flow_action_count **count,
+ int *fdb_mirror_limit,
struct rte_flow_error *error)
{
struct mlx5_priv *priv = dev->data->dev_private;
NULL,
"E-Switch must has a dest "
"port for mirroring");
+ if (!priv->config.hca_attr.reg_c_preserve &&
+ priv->representor_id != -1)
+ *fdb_mirror_limit = 1;
}
/* Continue validation for Xcap actions.*/
if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
uint16_t ether_type = 0;
int actions_n = 0;
uint8_t item_ipv6_proto = 0;
+ int fdb_mirror_limit = 0;
+ int modify_after_mirror = 0;
const struct rte_flow_item *geneve_item = NULL;
const struct rte_flow_item *gre_item = NULL;
const struct rte_flow_item *gtp_item = NULL;
++actions_n;
action_flags |= MLX5_FLOW_ACTION_FLAG |
MLX5_FLOW_ACTION_MARK_EXT;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
+
} else {
action_flags |= MLX5_FLOW_ACTION_FLAG;
++actions_n;
++actions_n;
action_flags |= MLX5_FLOW_ACTION_MARK |
MLX5_FLOW_ACTION_MARK_EXT;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
} else {
action_flags |= MLX5_FLOW_ACTION_MARK;
++actions_n;
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= MLX5_FLOW_ACTION_SET_META;
rw_act_num += MLX5_ACT_NUM_SET_META;
break;
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= MLX5_FLOW_ACTION_SET_TAG;
rw_act_num += MLX5_ACT_NUM_SET_TAG;
break;
RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
MLX5_FLOW_ACTION_SET_MAC_SRC :
MLX5_FLOW_ACTION_SET_MAC_DST;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
/*
* Even if the source and destination MAC addresses have
* overlap in the header with 4B alignment, the convert
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= actions->type ==
RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
MLX5_FLOW_ACTION_SET_IPV4_SRC :
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= actions->type ==
RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
MLX5_FLOW_ACTION_SET_IPV6_SRC :
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= actions->type ==
RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
MLX5_FLOW_ACTION_SET_TP_SRC :
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= actions->type ==
RTE_FLOW_ACTION_TYPE_SET_TTL ?
MLX5_FLOW_ACTION_SET_TTL :
error);
if (ret)
return ret;
+ if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
+ fdb_mirror_limit)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "sample and jump action combination is not supported");
++actions_n;
action_flags |= MLX5_FLOW_ACTION_JUMP;
break;
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= actions->type ==
RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
MLX5_FLOW_ACTION_INC_TCP_SEQ :
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= actions->type ==
RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
MLX5_FLOW_ACTION_INC_TCP_ACK :
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
rw_act_num += MLX5_ACT_NUM_SET_DSCP;
break;
/* Count all modify-header actions as one action. */
if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
++actions_n;
+ if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
+ modify_after_mirror = 1;
action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
rw_act_num += MLX5_ACT_NUM_SET_DSCP;
break;
attr, item_flags,
rss, &sample_rss,
&sample_count,
+ &fdb_mirror_limit,
error);
if (ret < 0)
return ret;
action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
break;
case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
- if (!attr->transfer && !attr->group)
- return rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_ACTION,
- NULL, "modify field action "
- "is not supported for group 0");
- ret = flow_dv_validate_action_modify_field(action_flags,
- actions,
- error);
+ ret = flow_dv_validate_action_modify_field(dev,
+ action_flags,
+ actions,
+ attr,
+ error);
if (ret < 0)
return ret;
/* Count all modify-header actions as one action. */
NULL, "too many header modify"
" actions to support");
}
+ /* Eswitch egress mirror and modify flow has limitation on CX5 */
+ if (fdb_mirror_limit && modify_after_mirror)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION, NULL,
+ "sample before modify action is not supported");
return 0;
}
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ACTION, NULL,
"invalid shared action to update");
+ if (priv->obj_ops.ind_table_modify == NULL)
+ return rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION, NULL,
+ "cannot modify indirection table");
queue = mlx5_malloc(MLX5_MEM_ZERO,
RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
0, SOCKET_ID_ANY);
RTE_SET_USED(conf);
switch (action->type) {
case RTE_FLOW_ACTION_TYPE_RSS:
+ /*
+ * priv->obj_ops is set according to driver capabilities.
+ * When DevX capabilities are
+ * sufficient, it is set to devx_obj_ops.
+ * Otherwise, it is set to ibv_obj_ops.
+ * ibv_obj_ops doesn't support ind_table_modify operation.
+ * In this case the shared RSS action can't be used.
+ */
+ if (priv->obj_ops.ind_table_modify == NULL)
+ return rte_flow_error_set
+ (err, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL,
+ "shared RSS action not supported");
return mlx5_validate_action_rss(dev, action, err);
case RTE_FLOW_ACTION_TYPE_AGE:
if (!priv->sh->aso_age_mng)
git.droids-corp.org / dpdk.git / blobdiff