net/mlx5: fix DevX Rx queue memory alignment

[dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 3f73a28..42ead7d 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -155,6 +155,21 @@
 /* Tunnel packet bit in the CQE. */
 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 
+/* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
+#define MLX5_CQE_LRO_PUSH_MASK 0x40
+
+/* Mask for L4 type in the CQE hdr_type_etc field. */
+#define MLX5_CQE_L4_TYPE_MASK 0x70
+
+/* The bit index of L4 type in CQE hdr_type_etc field. */
+#define MLX5_CQE_L4_TYPE_SHIFT 0x4
+
+/* L4 type to indicate TCP packet without acknowledgment. */
+#define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
+
+/* L4 type to indicate TCP packet with acknowledgment. */
+#define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
+
 /* Inner L3 checksum offload (Tunneled packets only). */
 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 
@@ -222,6 +237,12 @@
 /* Amount of data bytes after eth data segment. */
 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 
+/* The maximum log value of segments per RQ WQE. */
+#define MLX5_MAX_LOG_RQ_SEGS 5u
+
+/* The alignment needed for WQ buffer. */
+#define MLX5_WQE_BUF_ALIGNMENT 512
+
 /* Completion mode. */
 enum mlx5_completion_mode {
        MLX5_COMP_ONLY_ERR = 0x0,
@@ -1450,6 +1471,11 @@ enum {
        MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
 };
 
+enum {
+       MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
+       MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
+};
+
 struct mlx5_ifc_tirc_bits {
        u8 reserved_at_0[0x20];
        u8 disp_type[0x4];