net/mlx5: fix DevX Rx queue memory alignment

[dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 970dee0..42ead7d 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -155,6 +155,21 @@
 /* Tunnel packet bit in the CQE. */
 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 
+/* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
+#define MLX5_CQE_LRO_PUSH_MASK 0x40
+
+/* Mask for L4 type in the CQE hdr_type_etc field. */
+#define MLX5_CQE_L4_TYPE_MASK 0x70
+
+/* The bit index of L4 type in CQE hdr_type_etc field. */
+#define MLX5_CQE_L4_TYPE_SHIFT 0x4
+
+/* L4 type to indicate TCP packet without acknowledgment. */
+#define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
+
+/* L4 type to indicate TCP packet with acknowledgment. */
+#define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
+
 /* Inner L3 checksum offload (Tunneled packets only). */
 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 
@@ -222,6 +237,12 @@
 /* Amount of data bytes after eth data segment. */
 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 
+/* The maximum log value of segments per RQ WQE. */
+#define MLX5_MAX_LOG_RQ_SEGS 5u
+
+/* The alignment needed for WQ buffer. */
+#define MLX5_WQE_BUF_ALIGNMENT 512
+
 /* Completion mode. */
 enum mlx5_completion_mode {
        MLX5_COMP_ONLY_ERR = 0x0,
@@ -317,13 +338,19 @@ struct mlx5_cqe {
        uint8_t pkt_info;
        uint8_t rsvd0;
        uint16_t wqe_id;
-       uint8_t rsvd3[8];
+       uint8_t lro_tcppsh_abort_dupack;
+       uint8_t lro_min_ttl;
+       uint16_t lro_tcp_win;
+       uint32_t lro_ack_seq_num;
        uint32_t rx_hash_res;
        uint8_t rx_hash_type;
-       uint8_t rsvd1[11];
+       uint8_t rsvd1[3];
+       uint16_t csum;
+       uint8_t rsvd2[6];
        uint16_t hdr_type_etc;
        uint16_t vlan_info;
-       uint8_t rsvd2[12];
+       uint8_t lro_num_seg;
+       uint8_t rsvd3[11];
        uint32_t byte_cnt;
        uint64_t timestamp;
        uint32_t sop_drop_qpn;
@@ -631,6 +658,7 @@ enum {
        MLX5_CMD_OP_CREATE_RQ = 0x908,
        MLX5_CMD_OP_MODIFY_RQ = 0x909,
        MLX5_CMD_OP_QUERY_TIS = 0x915,
+       MLX5_CMD_OP_CREATE_RQT = 0x916,
        MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
        MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 };
@@ -1443,6 +1471,11 @@ enum {
        MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
 };
 
+enum {
+       MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
+       MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
+};
+
 struct mlx5_ifc_tirc_bits {
        u8 reserved_at_0[0x20];
        u8 disp_type[0x4];
@@ -1488,6 +1521,45 @@ struct mlx5_ifc_create_tir_in_bits {
        struct mlx5_ifc_tirc_bits ctx;
 };
 
+struct mlx5_ifc_rq_num_bits {
+       u8 reserved_at_0[0x8];
+       u8 rq_num[0x18];
+};
+
+struct mlx5_ifc_rqtc_bits {
+       u8 reserved_at_0[0xa0];
+       u8 reserved_at_a0[0x10];
+       u8 rqt_max_size[0x10];
+       u8 reserved_at_c0[0x10];
+       u8 rqt_actual_size[0x10];
+       u8 reserved_at_e0[0x6a0];
+       struct mlx5_ifc_rq_num_bits rq_num[];
+};
+
+struct mlx5_ifc_create_rqt_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x8];
+       u8 rqtn[0x18];
+       u8 reserved_at_60[0x20];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_create_rqt_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0xc0];
+       struct mlx5_ifc_rqtc_bits rqt_context;
+};
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
 /* CQE format mask. */
 #define MLX5E_CQE_FORMAT_MASK 0xc