net/mlx5: accelerate DV flow counter transactions

[dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 7482383..79f852b 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -415,6 +415,14 @@ typedef uint8_t u8;
                                 (((_v) & __mlx5_mask(typ, fld)) << \
                                   __mlx5_dw_bit_off(typ, fld))); \
        } while (0)
+
+#define MLX5_SET64(typ, p, fld, v) \
+       do { \
+               assert(__mlx5_bit_sz(typ, fld) == 64); \
+               *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
+                       rte_cpu_to_be_64(v); \
+       } while (0)
+
 #define MLX5_GET(typ, p, fld) \
        ((rte_be_to_cpu_32(*((__be32 *)(p) +\
        __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
@@ -428,7 +436,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-       u8 reserved_at_0[0x8];
+       u8 gre_c_present[0x1];
+       u8 reserved_at_1[0x1];
+       u8 gre_k_present[0x1];
+       u8 gre_s_present[0x1];
+       u8 source_vhci_port[0x4];
        u8 source_sqn[0x18];
        u8 reserved_at_20[0x10];
        u8 source_port[0x10];
@@ -552,10 +564,15 @@ enum {
 
 enum {
        MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
+       MLX5_CMD_OP_CREATE_MKEY = 0x200,
        MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
        MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 };
 
+enum {
+       MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
+};
+
 /* Flow counters. */
 struct mlx5_ifc_alloc_flow_counter_out_bits {
        u8         status[0x8];
@@ -570,7 +587,9 @@ struct mlx5_ifc_alloc_flow_counter_in_bits {
        u8         reserved_at_10[0x10];
        u8         reserved_at_20[0x10];
        u8         op_mod[0x10];
-       u8         reserved_at_40[0x40];
+       u8         flow_counter_id[0x20];
+       u8         reserved_at_40[0x18];
+       u8         flow_counter_bulk[0x8];
 };
 
 struct mlx5_ifc_dealloc_flow_counter_out_bits {
@@ -607,13 +626,102 @@ struct mlx5_ifc_query_flow_counter_in_bits {
        u8         reserved_at_10[0x10];
        u8         reserved_at_20[0x10];
        u8         op_mod[0x10];
-       u8         reserved_at_40[0x80];
+       u8         reserved_at_40[0x20];
+       u8         mkey[0x20];
+       u8         address[0x40];
        u8         clear[0x1];
-       u8         reserved_at_c1[0xf];
-       u8         num_of_counters[0x10];
+       u8         dump_to_memory[0x1];
+       u8         num_of_counters[0x1e];
        u8         flow_counter_id[0x20];
 };
 
+struct mlx5_ifc_mkc_bits {
+       u8         reserved_at_0[0x1];
+       u8         free[0x1];
+       u8         reserved_at_2[0x1];
+       u8         access_mode_4_2[0x3];
+       u8         reserved_at_6[0x7];
+       u8         relaxed_ordering_write[0x1];
+       u8         reserved_at_e[0x1];
+       u8         small_fence_on_rdma_read_response[0x1];
+       u8         umr_en[0x1];
+       u8         a[0x1];
+       u8         rw[0x1];
+       u8         rr[0x1];
+       u8         lw[0x1];
+       u8         lr[0x1];
+       u8         access_mode_1_0[0x2];
+       u8         reserved_at_18[0x8];
+
+       u8         qpn[0x18];
+       u8         mkey_7_0[0x8];
+
+       u8         reserved_at_40[0x20];
+
+       u8         length64[0x1];
+       u8         bsf_en[0x1];
+       u8         sync_umr[0x1];
+       u8         reserved_at_63[0x2];
+       u8         expected_sigerr_count[0x1];
+       u8         reserved_at_66[0x1];
+       u8         en_rinval[0x1];
+       u8         pd[0x18];
+
+       u8         start_addr[0x40];
+
+       u8         len[0x40];
+
+       u8         bsf_octword_size[0x20];
+
+       u8         reserved_at_120[0x80];
+
+       u8         translations_octword_size[0x20];
+
+       u8         reserved_at_1c0[0x1b];
+       u8         log_page_size[0x5];
+
+       u8         reserved_at_1e0[0x20];
+};
+
+struct mlx5_ifc_create_mkey_out_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+
+       u8         syndrome[0x20];
+
+       u8         reserved_at_40[0x8];
+       u8         mkey_index[0x18];
+
+       u8         reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_mkey_in_bits {
+       u8         opcode[0x10];
+       u8         reserved_at_10[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         op_mod[0x10];
+
+       u8         reserved_at_40[0x20];
+
+       u8         pg_access[0x1];
+       u8         reserved_at_61[0x1f];
+
+       struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
+
+       u8         reserved_at_280[0x80];
+
+       u8         translations_octword_actual_size[0x20];
+
+       u8         mkey_umem_id[0x20];
+
+       u8         mkey_umem_offset[0x40];
+
+       u8         reserved_at_380[0x500];
+
+       u8         klm_pas_mtt[][0x20];
+};
+
 enum {
        MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
        MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP        = 0xc << 1,