net/mlx5: query HCA for enabled FLEX parser protocols

[dpdk.git] / drivers / net / mlx5 / mlx5_prm.h

diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index b0e281f..e429792 100644 (file)
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -72,9 +72,8 @@
  * boundary with accounting the title Control and Ethernet
  * segments.
  */
-#define MLX5_EMPW_DEF_INLINE_LEN (3U * MLX5_WQE_SIZE + \
-                                 MLX5_DSEG_MIN_INLINE_SIZE - \
-                                 MLX5_WQE_DSEG_SIZE)
+#define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
+                                 MLX5_DSEG_MIN_INLINE_SIZE)
 /*
  * Maximal inline data length sent with enhanced MPW.
  * Is based on maximal WQE size.
@@ -90,11 +89,16 @@
  * If there are no enough resources to built minimal
  * EMPW the sending loop exits.
  */
-#define MLX5_EMPW_MIN_PACKETS (2 + 3 * 4)
-#define MLX5_EMPW_MAX_PACKETS ((MLX5_WQE_SIZE_MAX - \
-                               MLX5_WQE_CSEG_SIZE - \
-                               MLX5_WQE_ESEG_SIZE) / \
-                               MLX5_WSEG_SIZE)
+#define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
+/*
+ * Maximal amount of packets to be sent with EMPW.
+ * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
+ * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
+ * without CQE generation request, being multiplied by
+ * MLX5_TX_COMP_MAX_CQE it may cause significant latency
+ * in tx burst routine at the moment of freeing multiple mbufs.
+ */
+#define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
 /*
  * Default packet length threshold to be inlined with
  * ordinary SEND. Inlining saves the MR key search
@@ -155,6 +159,21 @@
 /* Tunnel packet bit in the CQE. */
 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 
+/* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
+#define MLX5_CQE_LRO_PUSH_MASK 0x40
+
+/* Mask for L4 type in the CQE hdr_type_etc field. */
+#define MLX5_CQE_L4_TYPE_MASK 0x70
+
+/* The bit index of L4 type in CQE hdr_type_etc field. */
+#define MLX5_CQE_L4_TYPE_SHIFT 0x4
+
+/* L4 type to indicate TCP packet without acknowledgment. */
+#define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
+
+/* L4 type to indicate TCP packet with acknowledgment. */
+#define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
+
 /* Inner L3 checksum offload (Tunneled packets only). */
 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 
@@ -222,6 +241,12 @@
 /* Amount of data bytes after eth data segment. */
 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 
+/* The maximum log value of segments per RQ WQE. */
+#define MLX5_MAX_LOG_RQ_SEGS 5u
+
+/* The alignment needed for WQ buffer. */
+#define MLX5_WQE_BUF_ALIGNMENT 512
+
 /* Completion mode. */
 enum mlx5_completion_mode {
        MLX5_COMP_ONLY_ERR = 0x0,
@@ -317,13 +342,19 @@ struct mlx5_cqe {
        uint8_t pkt_info;
        uint8_t rsvd0;
        uint16_t wqe_id;
-       uint8_t rsvd3[8];
+       uint8_t lro_tcppsh_abort_dupack;
+       uint8_t lro_min_ttl;
+       uint16_t lro_tcp_win;
+       uint32_t lro_ack_seq_num;
        uint32_t rx_hash_res;
        uint8_t rx_hash_type;
-       uint8_t rsvd1[11];
+       uint8_t rsvd1[3];
+       uint16_t csum;
+       uint8_t rsvd2[6];
        uint16_t hdr_type_etc;
        uint16_t vlan_info;
-       uint8_t rsvd2[12];
+       uint8_t lro_num_seg;
+       uint8_t rsvd3[11];
        uint32_t byte_cnt;
        uint64_t timestamp;
        uint32_t sop_drop_qpn;
@@ -382,6 +413,7 @@ enum mlx5_modification_field {
        MLX5_MODI_OUT_DIPV6_31_0,
        MLX5_MODI_OUT_SIPV4,
        MLX5_MODI_OUT_DIPV4,
+       MLX5_MODI_OUT_FIRST_VID,
        MLX5_MODI_IN_SMAC_47_16 = 0x31,
        MLX5_MODI_IN_SMAC_15_0,
        MLX5_MODI_IN_ETHERTYPE,
@@ -582,7 +614,14 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
        struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
        struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
        struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
-       u8 reserved_at_80[0x100];
+       u8 metadata_reg_c_7[0x20];
+       u8 metadata_reg_c_6[0x20];
+       u8 metadata_reg_c_5[0x20];
+       u8 metadata_reg_c_4[0x20];
+       u8 metadata_reg_c_3[0x20];
+       u8 metadata_reg_c_2[0x20];
+       u8 metadata_reg_c_1[0x20];
+       u8 metadata_reg_c_0[0x20];
        u8 metadata_reg_a[0x20];
        u8 reserved_at_1a0[0x60];
 };
@@ -817,6 +856,18 @@ enum {
        MLX5_INLINE_MODE_INNER_TCP_UDP,
 };
 
+/* HCA bit masks indicating which Flex parser protocols are already enabled. */
+#define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
+#define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
+#define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
+#define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
+#define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
+#define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
+#define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
+#define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
+#define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
+#define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
+
 struct mlx5_ifc_cmd_hca_cap_bits {
        u8 reserved_at_0[0x30];
        u8 vhca_id[0x10];
@@ -1444,6 +1495,11 @@ enum {
        MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
 };
 
+enum {
+       MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
+       MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
+};
+
 struct mlx5_ifc_tirc_bits {
        u8 reserved_at_0[0x20];
        u8 disp_type[0x4];