net/mlx5: support metadata as flow rule criteria

[dpdk.git] / drivers / net / mlx5 / mlx5_rxq.c

diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index 071740b..ed993ea 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -388,7 +388,6 @@ mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
                             DEV_RX_OFFLOAD_TIMESTAMP |
                             DEV_RX_OFFLOAD_JUMBO_FRAME);
 
-       offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
        if (config->hw_fcs_strip)
                offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 
@@ -647,7 +646,8 @@ mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
        doorbell = (uint64_t)doorbell_hi << 32;
        doorbell |=  rxq->cqn;
        rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
-       rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
+       mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
+                        cq_db_reg, rxq->uar_lock_cq);
 }
 
 /**
@@ -1233,6 +1233,13 @@ mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
         */
        desc *= 4;
        obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
+       /*
+        * rte_mempool_create_empty() has sanity check to refuse large cache
+        * size compared to the number of elements.
+        * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
+        * constant number 2 instead.
+        */
+       obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
        /* Check a mempool is already allocated and if it can be resued. */
        if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
                DRV_LOG(DEBUG, "port %u mempool %s is being reused",
@@ -1348,7 +1355,7 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
                sizeof(struct rte_mbuf_ext_shared_info) +
                RTE_PKTMBUF_HEADROOM;
        if (mprq_en &&
-           desc >= (1U << config->mprq.stride_num_n) &&
+           desc > (1U << config->mprq.stride_num_n) &&
            mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
                /* TODO: Rx scatter isn't supported yet. */
                tmpl->rxq.sges_n = 0;
@@ -1403,6 +1410,14 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
                        dev->data->dev_conf.rxmode.max_rx_pkt_len,
                        mb_len - RTE_PKTMBUF_HEADROOM);
        }
+       if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
+               DRV_LOG(WARNING,
+                       "port %u MPRQ is requested but cannot be enabled"
+                       " (requested: desc = %u, stride_sz = %u,"
+                       " supported: min_stride_num = %u, max_stride_sz = %u).",
+                       dev->data->port_id, desc, mprq_stride_size,
+                       (1 << config->mprq.stride_num_n),
+                       (1 << config->mprq.max_stride_size_n));
        DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
                dev->data->port_id, 1 << tmpl->rxq.sges_n);
        if (desc % (1 << tmpl->rxq.sges_n)) {
@@ -1422,7 +1437,7 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
        tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
        /* By default, FCS (CRC) is stripped by hardware. */
        tmpl->rxq.crc_present = 0;
-       if (rte_eth_dev_must_keep_crc(offloads)) {
+       if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
                if (config->hw_fcs_strip) {
                        tmpl->rxq.crc_present = 1;
                } else {
@@ -1449,6 +1464,9 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
        tmpl->rxq.elts_n = log2above(desc);
        tmpl->rxq.elts =
                (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
+#ifndef RTE_ARCH_64
+       tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
+#endif
        tmpl->idx = idx;
        rte_atomic32_inc(&tmpl->refcnt);
        LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
@@ -1748,7 +1766,8 @@ struct mlx5_hrxq *
 mlx5_hrxq_new(struct rte_eth_dev *dev,
              const uint8_t *rss_key, uint32_t rss_key_len,
              uint64_t hash_fields,
-             const uint16_t *queues, uint32_t queues_n)
+             const uint16_t *queues, uint32_t queues_n,
+             int tunnel __rte_unused)
 {
        struct priv *priv = dev->data->dev_private;
        struct mlx5_hrxq *hrxq;
@@ -1790,9 +1809,8 @@ mlx5_hrxq_new(struct rte_eth_dev *dev,
                        .pd = priv->pd,
                 },
                 &(struct mlx5dv_qp_init_attr){
-                       .comp_mask = (hash_fields & IBV_RX_HASH_INNER) ?
-                                MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS :
-                                0,
+                       .comp_mask = tunnel ?
+                               MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS : 0,
                        .create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS,
                 });
 #else