net/mlx5: support multi-packet send

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 6b3bb2d..41605f9 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -91,6 +91,15 @@ struct fdir_queue {
 
 struct priv;
 
+/* Compressed CQE context. */
+struct rxq_zip {
+       uint16_t ai; /* Array index. */
+       uint16_t ca; /* Current array index. */
+       uint16_t na; /* Next array index. */
+       uint16_t cq_ci; /* The next CQE. */
+       uint32_t cqe_cnt; /* Number of CQEs. */
+};
+
 /* RX queue descriptor. */
 struct rxq {
        unsigned int csum:1; /* Enable checksum offloading. */
@@ -100,9 +109,11 @@ struct rxq {
        uint16_t rq_ci;
        uint16_t cq_ci;
        uint16_t elts_n;
+       uint16_t cqe_n; /* Number of CQ elements. */
        uint16_t port_id;
        volatile struct mlx5_wqe_data_seg(*wqes)[];
        volatile struct mlx5_cqe(*cqes)[];
+       struct rxq_zip zip; /* Compressed context. */
        volatile uint32_t *rq_db;
        volatile uint32_t *cq_db;
        struct rte_mbuf *(*elts)[];
@@ -227,8 +238,7 @@ struct hash_rxq {
 struct txq {
        uint16_t elts_head; /* Current index in (*elts)[]. */
        uint16_t elts_tail; /* First element awaiting completion. */
-       uint16_t elts_comp_cd_init; /* Initial value for countdown. */
-       uint16_t elts_comp; /* Elements before asking a completion. */
+       uint16_t elts_comp; /* Counter since last completion request. */
        uint16_t elts_n; /* (*elts)[] length. */
        uint16_t cq_ci; /* Consumer index for completion queue. */
        uint16_t cqe_n; /* Number of CQ elements. */
@@ -236,6 +246,8 @@ struct txq {
        uint16_t wqe_n; /* Number of WQ elements. */
        uint16_t bf_offset; /* Blueflame offset. */
        uint16_t bf_buf_size; /* Blueflame size. */
+       uint16_t max_inline; /* Maximum size to inline in a WQE. */
+       uint32_t qp_num_8s; /* QP number shifted by 8. */
        volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
        volatile union mlx5_wqe (*wqes)[]; /* Work queue. */
        volatile uint32_t *qp_db; /* Work queue doorbell. */
@@ -248,7 +260,6 @@ struct txq {
        } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
        struct rte_mbuf *(*elts)[]; /* TX elements. */
        struct mlx5_txq_stats stats; /* TX queue counters. */
-       uint32_t qp_num_8s; /* QP number shifted by 8. */
 } __rte_cache_aligned;
 
 /* TX queue control descriptor. */
@@ -300,6 +311,9 @@ uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
 /* mlx5_rxtx.c */
 
 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
+uint16_t mlx5_tx_burst_inline(void *, struct rte_mbuf **, uint16_t);
+uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
+uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);