net/hns3: support flow director

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 9b58d0a..4f73d91 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -40,7 +40,7 @@
 #include "mlx5_glue.h"
 
 /* Support tunnel matching. */
-#define MLX5_FLOW_TUNNEL 6
+#define MLX5_FLOW_TUNNEL 8
 
 struct mlx5_rxq_stats {
 #ifdef MLX5_PMD_SOFT_COUNTERS
@@ -115,7 +115,8 @@ struct mlx5_rxq_data {
        unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
        unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
        unsigned int strd_headroom_en:1; /* Enable mbuf headroom in MPRQ. */
-       unsigned int :2; /* Remaining bits. */
+       unsigned int lro:1; /* Enable LRO. */
+       unsigned int :1; /* Remaining bits. */
        volatile uint32_t *rq_db;
        volatile uint32_t *cq_db;
        uint16_t port_id;
@@ -238,6 +239,7 @@ struct mlx5_txq_local {
        struct rte_mbuf *mbuf; /* first mbuf to process. */
        uint16_t pkts_copy; /* packets copied to elts. */
        uint16_t pkts_sent; /* packets sent. */
+       uint16_t pkts_loop; /* packets sent on loop entry. */
        uint16_t elts_free; /* available elts remain. */
        uint16_t wqe_free; /* available wqe remain. */
        uint16_t mbuf_off; /* data offset in current mbuf. */
@@ -367,9 +369,8 @@ int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
-uint64_t mlx5_get_rx_port_offloads(struct rte_eth_dev *dev);
+uint64_t mlx5_get_rx_port_offloads(void);
 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
-int mlx5_lro_on(struct rte_eth_dev *dev);
 
 /* mlx5_txq.c */
 
@@ -400,7 +401,7 @@ extern uint8_t mlx5_swp_types_table[];
 void mlx5_set_ptype_table(void);
 void mlx5_set_cksum_table(void);
 void mlx5_set_swp_types_table(void);
-__rte_noinline uint16_t mlx5_tx_error_cqe_handle
+__rte_noinline int mlx5_tx_error_cqe_handle
                                (struct mlx5_txq_data *restrict txq,
                                 volatile struct mlx5_err_cqe *err_cqe);
 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
@@ -499,9 +500,9 @@ __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
 
 /* CQE status. */
 enum mlx5_cqe_status {
-       MLX5_CQE_STATUS_SW_OWN,
-       MLX5_CQE_STATUS_HW_OWN,
-       MLX5_CQE_STATUS_ERR,
+       MLX5_CQE_STATUS_SW_OWN = -1,
+       MLX5_CQE_STATUS_HW_OWN = -2,
+       MLX5_CQE_STATUS_ERR = -3,
 };
 
 /**