net/mlx5: fix memory region cache last index

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 2eb2f05..7297f01 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -555,20 +555,18 @@ mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
        if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end >= addr))
                return txq->mp2mr[i]->lkey;
        for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
-               if (unlikely(txq->mp2mr[i]->mr == NULL)) {
+               if (unlikely(txq->mp2mr[i] == NULL ||
+                   txq->mp2mr[i]->mr == NULL)) {
                        /* Unknown MP, add a new MR for it. */
                        break;
                }
                if (txq->mp2mr[i]->start <= addr &&
                    txq->mp2mr[i]->end >= addr) {
                        assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
-                       assert(rte_cpu_to_be_32(txq->mp2mr[i]->mr->lkey) ==
-                              txq->mp2mr[i]->lkey);
                        txq->mr_cache_idx = i;
                        return txq->mp2mr[i]->lkey;
                }
        }
-       txq->mr_cache_idx = 0;
        mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
        /*
         * Request the reference to use in this queue, the original one is
@@ -576,7 +574,13 @@ mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
         */
        if (mr) {
                rte_atomic32_inc(&mr->refcnt);
+               txq->mr_cache_idx = i >= RTE_DIM(txq->mp2mr) ? i - 1 : i;
                return mr->lkey;
+       } else {
+               struct rte_mempool *mp = mlx5_tx_mb2mp(mb);
+
+               WARN("Failed to register mempool 0x%p(%s)",
+                     (void *)mp, mp->name);
        }
        return (uint32_t)-1;
 }
@@ -598,7 +602,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
        uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
        volatile uint64_t *src = ((volatile uint64_t *)wqe);
 
-       rte_io_wmb();
+       rte_cio_wmb();
        *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
        /* Ensure ordering between DB record and BF copy. */
        rte_wmb();