net/mlx5: replace network to host macros

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 7fd59a4..9375aa8 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -48,16 +48,10 @@
 #pragma GCC diagnostic error "-Wpedantic"
 #endif
 
-/* DPDK headers don't like -pedantic. */
-#ifdef PEDANTIC
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
 #include <rte_mbuf.h>
 #include <rte_mempool.h>
 #include <rte_common.h>
-#ifdef PEDANTIC
-#pragma GCC diagnostic error "-Wpedantic"
-#endif
+#include <rte_hexdump.h>
 
 #include "mlx5_utils.h"
 #include "mlx5.h"
@@ -81,7 +75,7 @@ struct mlx5_txq_stats {
        uint64_t opackets; /**< Total of successfully sent packets. */
        uint64_t obytes; /**< Total of successfully sent bytes. */
 #endif
-       uint64_t odropped; /**< Total of packets not sent when TX ring full. */
+       uint64_t oerrors; /**< Total number of failed transmitted packets. */
 };
 
 /* Flow director queue structure. */
@@ -116,8 +110,7 @@ struct rxq {
        unsigned int rss_hash:1; /* RSS hash result is enabled. */
        unsigned int mark:1; /* Marked flow available on the queue. */
        unsigned int pending_err:1; /* CQE error needs to be handled. */
-       unsigned int trim_elts:1; /* Whether elts needs clean-up. */
-       unsigned int :6; /* Remaining bits. */
+       unsigned int :7; /* Remaining bits. */
        volatile uint32_t *rq_db;
        volatile uint32_t *cq_db;
        uint16_t rq_ci;
@@ -276,7 +269,7 @@ struct txq {
                uintptr_t start; /* Start address of MR */
                uintptr_t end; /* End address of MR */
                struct ibv_mr *mr; /* Memory Region (for mp). */
-               uint32_t lkey; /* htonl(mr->lkey) */
+               uint32_t lkey; /* rte_cpu_to_be_32(mr->lkey) */
        } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
        uint16_t mr_cache_idx; /* Index of last hit entry. */
        struct rte_mbuf *(*elts)[]; /* TX elements. */
@@ -307,14 +300,9 @@ void priv_destroy_hash_rxqs(struct priv *);
 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
 int priv_rehash_flows(struct priv *);
 void rxq_cleanup(struct rxq_ctrl *);
-int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
-int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
-                  unsigned int, const struct rte_eth_rxconf *,
-                  struct rte_mempool *);
 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
                        const struct rte_eth_rxconf *, struct rte_mempool *);
 void mlx5_rx_queue_release(void *);
-uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
 int priv_rx_intr_vec_enable(struct priv *priv);
 void priv_rx_intr_vec_disable(struct priv *priv);
 #ifdef HAVE_UPDATE_CQ_CI
@@ -330,12 +318,12 @@ int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
                        const struct rte_eth_txconf *);
 void mlx5_tx_queue_release(void *);
-uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
 
 /* mlx5_rxtx.c */
 
-extern const uint32_t mlx5_ptype_table[];
+extern uint32_t mlx5_ptype_table[];
 
+void mlx5_set_ptype_table(void);
 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
@@ -351,7 +339,6 @@ int priv_check_raw_vec_tx_support(struct priv *);
 int priv_check_vec_tx_support(struct priv *);
 int rxq_check_vec_support(struct rxq *);
 int priv_check_vec_rx_support(struct priv *);
-void priv_prep_vec_rx_function(struct priv *);
 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
@@ -422,16 +409,24 @@ check_cqe(volatile struct mlx5_cqe *cqe,
                if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
                    (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
                        return 0;
-               if (!check_cqe_seen(cqe))
+               if (!check_cqe_seen(cqe)) {
                        ERROR("unexpected CQE error %u (0x%02x)"
                              " syndrome 0x%02x",
                              op_code, op_code, syndrome);
+                       rte_hexdump(stderr, "MLX5 Error CQE:",
+                                   (const void *)((uintptr_t)err_cqe),
+                                   sizeof(*err_cqe));
+               }
                return 1;
        } else if ((op_code != MLX5_CQE_RESP_SEND) &&
                   (op_code != MLX5_CQE_REQ)) {
-               if (!check_cqe_seen(cqe))
+               if (!check_cqe_seen(cqe)) {
                        ERROR("unexpected CQE opcode %u (0x%02x)",
                              op_code, op_code);
+                       rte_hexdump(stderr, "MLX5 CQE:",
+                                   (const void *)((uintptr_t)cqe),
+                                   sizeof(*cqe));
+               }
                return 1;
        }
 #endif /* NDEBUG */
@@ -486,13 +481,18 @@ mlx5_tx_complete(struct txq *txq)
 #ifndef NDEBUG
        if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
            (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
-               if (!check_cqe_seen(cqe))
+               if (!check_cqe_seen(cqe)) {
                        ERROR("unexpected error CQE, TX stopped");
+                       rte_hexdump(stderr, "MLX5 TXQ:",
+                                   (const void *)((uintptr_t)txq->wqes),
+                                   ((1 << txq->wqe_n) *
+                                    MLX5_WQE_SIZE));
+               }
                return;
        }
 #endif /* NDEBUG */
        ++cq_ci;
-       txq->wqe_pi = ntohs(cqe->wqe_counter);
+       txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
        ctrl = (volatile struct mlx5_wqe_ctrl *)
                tx_mlx5_wqe(txq, txq->wqe_pi);
        elts_tail = ctrl->ctrl3;
@@ -530,7 +530,7 @@ mlx5_tx_complete(struct txq *txq)
        txq->elts_tail = elts_tail;
        /* Update the consumer index. */
        rte_wmb();
-       *txq->cq_db = htonl(cq_ci);
+       *txq->cq_db = rte_cpu_to_be_32(cq_ci);
 }
 
 /**
@@ -581,7 +581,7 @@ mlx5_tx_mb2mr(struct txq *txq, struct rte_mbuf *mb)
                if (txq->mp2mr[i].start <= addr &&
                    txq->mp2mr[i].end >= addr) {
                        assert(txq->mp2mr[i].lkey != (uint32_t)-1);
-                       assert(htonl(txq->mp2mr[i].mr->lkey) ==
+                       assert(rte_cpu_to_be_32(txq->mp2mr[i].mr->lkey) ==
                               txq->mp2mr[i].lkey);
                        txq->mr_cache_idx = i;
                        return txq->mp2mr[i].lkey;
@@ -605,8 +605,8 @@ mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
        uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
        volatile uint64_t *src = ((volatile uint64_t *)wqe);
 
-       rte_wmb();
-       *txq->qp_db = htonl(txq->wqe_ci);
+       rte_io_wmb();
+       *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
        /* Ensure ordering between DB record and BF copy. */
        rte_wmb();
        *dst = *src;