net/mlx5: fix xstats reset reinitialization

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx.h

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 164f36b..bcb1595 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -68,7 +68,7 @@ struct rxq_zip {
 /* Multi-Packet RQ buffer header. */
 struct mlx5_mprq_buf {
        struct rte_mempool *mp;
-       rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
+       uint16_t refcnt; /* Atomically accessed refcnt. */
        uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
        struct rte_mbuf_ext_shared_info shinfos[];
        /*
@@ -151,6 +151,8 @@ struct mlx5_rxq_data {
        /* CQ (UAR) access lock required for 32bit implementations */
 #endif
        uint32_t tunnel; /* Tunnel information. */
+       int timestamp_offset; /* Dynamic mbuf field for timestamp. */
+       uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */
        uint64_t flow_meta_mask;
        int32_t flow_meta_offset;
 } __rte_cache_aligned;
@@ -165,7 +167,7 @@ enum mlx5_rxq_type {
 struct mlx5_rxq_ctrl {
        struct mlx5_rxq_data rxq; /* Data path structure. */
        LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
-       rte_atomic32_t refcnt; /* Reference counter. */
+       uint32_t refcnt; /* Reference counter. */
        struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
        struct mlx5_priv *priv; /* Back pointer to private data. */
        enum mlx5_rxq_type type; /* Rxq type. */
@@ -261,55 +263,15 @@ struct mlx5_txq_data {
        /* Storage for queued packets, must be the last field. */
 } __rte_cache_aligned;
 
-enum mlx5_txq_obj_type {
-       MLX5_TXQ_OBJ_TYPE_IBV,          /* mlx5_txq_obj with ibv_wq. */
-       MLX5_TXQ_OBJ_TYPE_DEVX_SQ,      /* mlx5_txq_obj with mlx5_devx_sq. */
-       MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
-       /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
-};
-
 enum mlx5_txq_type {
        MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
        MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
 };
 
-/* Verbs/DevX Tx queue elements. */
-struct mlx5_txq_obj {
-       LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
-       rte_atomic32_t refcnt; /* Reference counter. */
-       struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
-       enum mlx5_txq_obj_type type; /* The txq object type. */
-       RTE_STD_C11
-       union {
-               struct {
-                       void *cq; /* Completion Queue. */
-                       void *qp; /* Queue Pair. */
-               };
-               struct {
-                       struct mlx5_devx_obj *sq;
-                       /* DevX object for Sx queue. */
-                       struct mlx5_devx_obj *tis; /* The TIS object. */
-               };
-               struct {
-                       struct rte_eth_dev *dev;
-                       struct mlx5_devx_obj *cq_devx;
-                       void *cq_umem;
-                       void *cq_buf;
-                       int64_t cq_dbrec_offset;
-                       struct mlx5_devx_dbr_page *cq_dbrec_page;
-                       struct mlx5_devx_obj *sq_devx;
-                       void *sq_umem;
-                       void *sq_buf;
-                       int64_t sq_dbrec_offset;
-                       struct mlx5_devx_dbr_page *sq_dbrec_page;
-               };
-       };
-};
-
 /* TX queue control descriptor. */
 struct mlx5_txq_ctrl {
        LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
-       rte_atomic32_t refcnt; /* Reference counter. */
+       uint32_t refcnt; /* Reference counter. */
        unsigned int socket; /* CPU socket ID for allocations. */
        enum mlx5_txq_type type; /* The txq ctrl type. */
        unsigned int max_inline_data; /* Max inline data. */
@@ -382,8 +344,8 @@ uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
-struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
-void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
+struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev);
+void mlx5_drop_action_destroy(struct rte_eth_dev *dev);
 uint64_t mlx5_get_rx_port_offloads(void);
 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
@@ -401,12 +363,9 @@ int mlx5_tx_hairpin_queue_setup
        (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
         const struct rte_eth_hairpin_conf *hairpin_conf);
 void mlx5_tx_queue_release(void *dpdk_txq);
+void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl);
 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
-struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
-                                     enum mlx5_txq_obj_type type);
-struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
-int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
                                   uint16_t desc, unsigned int socket,
@@ -627,7 +586,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
        uint64_t *dst = MLX5_TX_BFREG(txq);
        volatile uint64_t *src = ((volatile uint64_t *)wqe);
 
-       rte_cio_wmb();
+       rte_io_wmb();
        *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
        /* Ensure ordering between DB record and BF copy. */
        rte_wmb();
@@ -724,4 +683,21 @@ mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
        return ci;
 }
 
+/**
+ * Set timestamp in mbuf dynamic field.
+ *
+ * @param mbuf
+ *   Structure to write into.
+ * @param offset
+ *   Dynamic field offset in mbuf structure.
+ * @param timestamp
+ *   Value to write.
+ */
+static __rte_always_inline void
+mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,
+               rte_mbuf_timestamp_t timestamp)
+{
+       *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp;
+}
+
 #endif /* RTE_PMD_MLX5_RXTX_H_ */