net/mlx5: support Direct Rules E-Switch

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx_vec.h

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.h b/drivers/net/mlx5/mlx5_rxtx_vec.h
index fb884f9..4220b08 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx_vec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.h
@@ -22,6 +22,7 @@
 /* HW offload capabilities of vectorized Tx. */
 #define MLX5_VEC_TX_OFFLOAD_CAP \
        (MLX5_VEC_TX_CKSUM_OFFLOAD_CAP | \
+        DEV_TX_OFFLOAD_MATCH_METADATA | \
         DEV_TX_OFFLOAD_MULTI_SEGS)
 
 /*
@@ -101,7 +102,22 @@ mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
                return;
        }
        for (i = 0; i < n; ++i) {
-               wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
+               void *buf_addr;
+
+               /*
+                * Load the virtual address for Rx WQE. non-x86 processors
+                * (mostly RISC such as ARM and Power) are more vulnerable to
+                * load stall. For x86, reducing the number of instructions
+                * seems to matter most.
+                */
+#ifdef RTE_ARCH_X86_64
+               buf_addr = elts[i]->buf_addr;
+               assert(buf_addr == rte_mbuf_buf_addr(elts[i], rxq->mp));
+#else
+               buf_addr = rte_mbuf_buf_addr(elts[i], rxq->mp);
+               assert(buf_addr == elts[i]->buf_addr);
+#endif
+               wq[i].addr = rte_cpu_to_be_64((uintptr_t)buf_addr +
                                              RTE_PKTMBUF_HEADROOM);
                /* If there's only one MR, no need to replace LKey in WQE. */
                if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))