net/mlx5: add C++ include guard to public header

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx_vec_altivec.h

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
index bcf487c..f6e434c 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
@@ -974,10 +974,10 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                        (vector unsigned short)cqe_tmp1, cqe_sel_mask1);
                cqe_tmp2 = (vector unsigned char)(vector unsigned long){
                        *(__rte_aligned(8) unsigned long *)
-                       &cq[pos + p3].rsvd3[9], 0LL};
+                       &cq[pos + p3].rsvd4[2], 0LL};
                cqe_tmp1 = (vector unsigned char)(vector unsigned long){
                        *(__rte_aligned(8) unsigned long *)
-                       &cq[pos + p2].rsvd3[9], 0LL};
+                       &cq[pos + p2].rsvd4[2], 0LL};
                cqes[3] = (vector unsigned char)
                        vec_sel((vector unsigned short)cqes[3],
                        (vector unsigned short)cqe_tmp2,
@@ -1037,10 +1037,10 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                        (vector unsigned short)cqe_tmp1, cqe_sel_mask1);
                cqe_tmp2 = (vector unsigned char)(vector unsigned long){
                        *(__rte_aligned(8) unsigned long *)
-                       &cq[pos + p1].rsvd3[9], 0LL};
+                       &cq[pos + p1].rsvd4[2], 0LL};
                cqe_tmp1 = (vector unsigned char)(vector unsigned long){
                        *(__rte_aligned(8) unsigned long *)
-                       &cq[pos].rsvd3[9], 0LL};
+                       &cq[pos].rsvd4[2], 0LL};
                cqes[1] = (vector unsigned char)
                        vec_sel((vector unsigned short)cqes[1],
                        (vector unsigned short)cqe_tmp2, cqe_sel_mask2);
@@ -1189,6 +1189,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
 
                /* D.5 fill in mbuf - rearm_data and packet_type. */
                rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
+               if (unlikely(rxq->shared)) {
+                       pkts[pos]->port = cq[pos].user_index_low;
+                       pkts[pos + p1]->port = cq[pos + p1].user_index_low;
+                       pkts[pos + p2]->port = cq[pos + p2].user_index_low;
+                       pkts[pos + p3]->port = cq[pos + p3].user_index_low;
+               }
                if (rxq->hw_timestamp) {
                        int offset = rxq->timestamp_offset;
                        if (rxq->rt_timestamp) {
@@ -1224,7 +1230,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                        uint32_t mask = rxq->flow_meta_port_mask;
                        uint32_t metadata;
 
-                       /* This code is subject for futher optimization. */
+                       /* This code is subject for further optimization. */
                        metadata = rte_be_to_cpu_32
                                (cq[pos].flow_table_metadata) & mask;
                        *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =