net/mlx5: fix Tx checksum offloads
[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx_vec_neon.h
index 4cb7f28..77ce0c3 100644 (file)
@@ -60,7 +60,7 @@
  * @param txq
  *   Pointer to TX queue structure.
  * @param dseg
- *   Pointer to buffer descriptor to be writen.
+ *   Pointer to buffer descriptor to be written.
  * @param pkts
  *   Pointer to array of packets to be sent.
  * @param n
@@ -149,7 +149,7 @@ txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
                        11, 10,  9,  8, /* bswap32 */
                        12, 13, 14, 15
                };
-               uint8_t cs_flags = 0;
+               uint8_t cs_flags;
                uint16_t max_elts;
                uint16_t max_wqe;
                uint8x16_t *t_wqe;
@@ -168,22 +168,7 @@ txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
                        break;
                wqe = &((volatile struct mlx5_wqe64 *)
                         txq->wqes)[wqe_ci & wq_mask].hdr;
-               if (buf->ol_flags &
-                    (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
-                       const uint64_t is_tunneled =
-                               buf->ol_flags & (PKT_TX_TUNNEL_GRE |
-                                                PKT_TX_TUNNEL_VXLAN);
-
-                       if (is_tunneled && txq->tunnel_en) {
-                               cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
-                                          MLX5_ETH_WQE_L4_INNER_CSUM;
-                               if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
-                                       cs_flags |= MLX5_ETH_WQE_L3_CSUM;
-                       } else {
-                               cs_flags = MLX5_ETH_WQE_L3_CSUM |
-                                          MLX5_ETH_WQE_L4_CSUM;
-                       }
-               }
+               cs_flags = txq_ol_cksum_to_cs(txq, buf);
                /* Title WQEBB pointer. */
                t_wqe = (uint8x16_t *)wqe;
                dseg = (uint8_t *)(wqe + 1);
@@ -345,7 +330,7 @@ txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
        txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
                       nb_dword_per_wqebb;
        /* Ring QP doorbell. */
-       mlx5_tx_dbrec(txq, wqe);
+       mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
        return pkts_n;
 }
 
@@ -572,7 +557,7 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
        const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
        const uint8x16_t cv_flag_sel = {
                0,
-               (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
+               (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
                (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
                0,
                (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
@@ -582,7 +567,7 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
        };
        const uint32x4_t cv_mask =
                vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
-                           PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
+                           PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
        const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
        const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
        uint64x2_t rearm0, rearm1, rearm2, rearm3;