-1UL << ((mcqe_n - pos) *
sizeof(uint16_t) * 8) : 0);
#endif
-
- if (!(pos & 0x7) && pos + 8 < mcqe_n)
- rte_prefetch0((void *)(cq + pos + 8));
+ for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
+ if (likely(pos + i < mcqe_n))
+ rte_prefetch0((void *)(cq + pos + i));
__asm__ volatile (
/* A.1 load mCQEs into a 128bit register. */
"ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
elts[pos + 2]->hash.fdir.hi = flow_tag;
elts[pos + 3]->hash.fdir.hi = flow_tag;
}
+ if (rte_flow_dynf_metadata_avail()) {
+ const uint32_t meta = *RTE_FLOW_DYNF_METADATA(t_pkt);
+
+ /* Check if title packet has valid metadata. */
+ if (meta) {
+ MLX5_ASSERT(t_pkt->ol_flags &
+ PKT_RX_DYNF_METADATA);
+ *RTE_FLOW_DYNF_METADATA(elts[pos]) = meta;
+ *RTE_FLOW_DYNF_METADATA(elts[pos + 1]) = meta;
+ *RTE_FLOW_DYNF_METADATA(elts[pos + 2]) = meta;
+ *RTE_FLOW_DYNF_METADATA(elts[pos + 3]) = meta;
+ }
+ }
pos += MLX5_VPMD_DESCS_PER_LOOP;
/* Move to next CQE and invalidate consumed CQEs. */
if (!(pos & 0x7) && pos < mcqe_n) {