if (!txq_ctrl)
continue;
- if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
+ if (!txq_ctrl->is_hairpin)
txq_alloc_elts(txq_ctrl);
MLX5_ASSERT(!txq_ctrl->obj);
txq_ctrl->obj = mlx5_malloc(flags, sizeof(struct mlx5_txq_obj),
txq_ctrl->obj = NULL;
goto error;
}
- if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
+ if (!txq_ctrl->is_hairpin) {
size_t size = txq_data->cqe_s * sizeof(*txq_data->fcqs);
txq_data->fcqs = mlx5_malloc(flags, size,
{
int ret = 0;
- if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {
+ if (!rxq_ctrl->is_hairpin) {
/*
* Pre-register the mempools. Regardless of whether
* the implicit registration is enabled or not,
txq_ctrl = mlx5_txq_get(dev, i);
if (!txq_ctrl)
continue;
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN ||
+ if (!txq_ctrl->is_hairpin ||
txq_ctrl->hairpin_conf.peers[0].port != self_port) {
mlx5_txq_release(dev, i);
continue;
if (!txq_ctrl)
continue;
/* Skip hairpin queues with other peer ports. */
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN ||
+ if (!txq_ctrl->is_hairpin ||
txq_ctrl->hairpin_conf.peers[0].port != self_port) {
mlx5_txq_release(dev, i);
continue;
return -rte_errno;
}
rxq_ctrl = rxq->ctrl;
- if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN ||
+ if (!rxq_ctrl->is_hairpin ||
rxq->hairpin_conf.peers[0].queue != i) {
rte_errno = ENOMEM;
DRV_LOG(ERR, "port %u Tx queue %d can't be binded to "
dev->data->port_id, peer_queue);
return -rte_errno;
}
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u queue %d is not a hairpin Txq",
dev->data->port_id, peer_queue);
return -rte_errno;
}
rxq_ctrl = rxq->ctrl;
- if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
+ if (!rxq_ctrl->is_hairpin) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u queue %d is not a hairpin Rxq",
dev->data->port_id, peer_queue);
dev->data->port_id, cur_queue);
return -rte_errno;
}
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u queue %d not a hairpin Txq",
dev->data->port_id, cur_queue);
return -rte_errno;
}
rxq_ctrl = rxq->ctrl;
- if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
+ if (!rxq_ctrl->is_hairpin) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u queue %d not a hairpin Rxq",
dev->data->port_id, cur_queue);
dev->data->port_id, cur_queue);
return -rte_errno;
}
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u queue %d not a hairpin Txq",
dev->data->port_id, cur_queue);
return -rte_errno;
}
rxq_ctrl = rxq->ctrl;
- if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {
+ if (!rxq_ctrl->is_hairpin) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u queue %d not a hairpin Rxq",
dev->data->port_id, cur_queue);
txq_ctrl = mlx5_txq_get(dev, i);
if (txq_ctrl == NULL)
continue;
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
mlx5_txq_release(dev, i);
continue;
}
txq_ctrl = mlx5_txq_get(dev, i);
if (txq_ctrl == NULL)
continue;
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
mlx5_txq_release(dev, i);
continue;
}
txq_ctrl = mlx5_txq_get(dev, i);
if (txq_ctrl == NULL)
continue;
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
mlx5_txq_release(dev, i);
continue;
}
txq_ctrl = mlx5_txq_get(dev, i);
if (!txq_ctrl)
continue;
- if (txq_ctrl->type != MLX5_TXQ_TYPE_HAIRPIN) {
+ if (!txq_ctrl->is_hairpin) {
mlx5_txq_release(dev, i);
continue;
}
if (rxq == NULL)
continue;
rxq_ctrl = rxq->ctrl;
- if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN)
+ if (!rxq_ctrl->is_hairpin)
continue;
pp = rxq->hairpin_conf.peers[0].port;
if (pp >= RTE_MAX_ETHPORTS) {
dev->data->port_id, strerror(rte_errno));
goto error;
}
- if ((priv->sh->cdev->config.devx && priv->config.dv_flow_en &&
- priv->config.dest_tir) && priv->obj_ops.lb_dummy_queue_create) {
+ if (mlx5_devx_obj_ops_en(priv->sh) &&
+ priv->obj_ops.lb_dummy_queue_create) {
ret = priv->obj_ops.lb_dummy_queue_create(dev);
if (ret)
goto error;
goto error;
}
if (priv->config.std_delay_drop || priv->config.hp_delay_drop) {
- if (!priv->config.vf && !priv->config.sf &&
+ if (!priv->sh->dev_cap.vf && !priv->sh->dev_cap.sf &&
!priv->representor) {
ret = mlx5_get_flag_dropless_rq(dev);
if (ret < 0)
priv->sh->port[priv->dev_port - 1].ih_port_id =
(uint32_t)dev->data->port_id;
} else {
- DRV_LOG(INFO, "port %u starts without LSC and RMV interrupts.",
+ DRV_LOG(INFO, "port %u starts without RMV interrupts.",
dev->data->port_id);
- dev->data->dev_conf.intr_conf.lsc = 0;
dev->data->dev_conf.intr_conf.rmv = 0;
}
+ if (rte_intr_fd_get(priv->sh->intr_handle_nl) >= 0) {
+ priv->sh->port[priv->dev_port - 1].nl_ih_port_id =
+ (uint32_t)dev->data->port_id;
+ } else {
+ DRV_LOG(INFO, "port %u starts without LSC interrupts.",
+ dev->data->port_id);
+ dev->data->dev_conf.intr_conf.lsc = 0;
+ }
if (rte_intr_fd_get(priv->sh->intr_handle_devx) >= 0)
priv->sh->port[priv->dev_port - 1].devx_ih_port_id =
(uint32_t)dev->data->port_id;
mlx5_rx_intr_vec_disable(dev);
priv->sh->port[priv->dev_port - 1].ih_port_id = RTE_MAX_ETHPORTS;
priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;
+ priv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS;
mlx5_txq_stop(dev);
mlx5_rxq_stop(dev);
if (priv->obj_ops.lb_dummy_queue_release)
* Enable traffic flows configured by control plane
*
* @param dev
- * Pointer to Ethernet device private data.
- * @param dev
* Pointer to Ethernet device structure.
*
* @return
if (!txq_ctrl)
continue;
/* Only Tx implicit mode requires the default Tx flow. */
- if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN &&
+ if (txq_ctrl->is_hairpin &&
txq_ctrl->hairpin_conf.tx_explicit == 0 &&
txq_ctrl->hairpin_conf.peers[0].port ==
priv->dev_data->port_id) {
goto error;
}
}
- if (priv->config.dv_esw_en) {
+ if (priv->sh->config.dv_esw_en) {
if (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) {
DRV_LOG(ERR,
"Port %u Tx queue %u SQ create representor devx default miss rule failed.",
}
mlx5_txq_release(dev, i);
}
- if (priv->config.dv_esw_en) {
+ if (priv->sh->config.dv_esw_en) {
if (mlx5_flow_create_esw_table_zero_flow(dev))
priv->fdb_def_rule = 1;
else
" configured - only Eswitch group 0 flows are"
" supported.", dev->data->port_id);
}
- if (!priv->config.lacp_by_user && priv->pf_bond >= 0) {
+ if (!priv->sh->config.lacp_by_user && priv->pf_bond >= 0) {
ret = mlx5_flow_lacp_miss(dev);
if (ret)
DRV_LOG(INFO, "port %u LACP rule cannot be created - "