#include <stdint.h>
#include <rte_ether.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include <rte_interrupts.h>
#include <rte_alarm.h>
#include <rte_malloc.h>
#include <mlx5_common_devx.h>
#include "mlx5.h"
-#include "mlx5_rxtx.h"
+#include "mlx5_rx.h"
+#include "mlx5_tx.h"
#include "mlx5_common_os.h"
static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t),
.pd = sh->pdn,
.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
},
+ .ts_format = mlx5_ts_format_conv(sh->sq_ts_format),
};
struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
struct mlx5_devx_cq_attr cq_attr = {
sq_attr.wq_attr.cd_slave = 1;
sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
sq_attr.wq_attr.pd = sh->pdn;
+ sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);
ret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size),
&sq_attr, sh->numa_node);
if (ret) {
{
/*
* The only CQE of Clock Queue is being continuously
- * update by hardware with soecified rate. We have to
- * read timestump and WQE completion index atomically.
+ * updated by hardware with specified rate. We must
+ * read timestamp and WQE completion index atomically.
*/
#if defined(RTE_ARCH_X86_64)
rte_int128_t src;
} to;
uint64_t ts;
uint16_t ci;
+ uint8_t opcode;
mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
- if (to.cts.op_own >> 4) {
- DRV_LOG(DEBUG, "Clock Queue error sync lost.");
- __atomic_fetch_add(&sh->txpp.err_clock_queue,
+ opcode = MLX5_CQE_OPCODE(to.cts.op_own);
+ if (opcode) {
+ if (opcode != MLX5_CQE_INVALID) {
+ /*
+ * Commit the error state if and only if
+ * we have got at least one actual completion.
+ */
+ DRV_LOG(DEBUG,
+ "Clock Queue error sync lost (%X).", opcode);
+ __atomic_fetch_add(&sh->txpp.err_clock_queue,
1, __ATOMIC_RELAXED);
- sh->txpp.sync_lost = 1;
+ sh->txpp.sync_lost = 1;
+ }
return;
}
ci = rte_be_to_cpu_16(to.cts.wqe_counter);