struct mlx5_priv *priv = dev->data->dev_private;
uint64_t offloads = (RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
RTE_ETH_TX_OFFLOAD_VLAN_INSERT);
- struct mlx5_dev_config *config = &priv->config;
+ struct mlx5_port_config *config = &priv->config;
struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;
if (dev_cap->hw_csum)
RTE_ETH_TX_OFFLOAD_TCP_CKSUM);
if (dev_cap->tso)
offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
- if (priv->sh->config.tx_pp)
+ if (priv->sh->config.tx_pp ||
+ priv->sh->cdev->config.hca_attr.wait_on_time)
offloads |= RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP;
if (dev_cap->swp) {
if (dev_cap->swp & MLX5_SW_PARSING_CSUM_CAP)
return -rte_errno;
}
- if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
+ if (txq_ctrl->is_hairpin)
return 0;
MLX5_ASSERT(ppriv);
/*
rte_errno = ENOMEM;
}
- if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
+ if (txq_ctrl->is_hairpin)
return;
addr = ppriv->uar_table[txq_ctrl->txq.idx].db;
rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
continue;
txq = (*priv->txqs)[i];
txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
- if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
+ if (txq_ctrl->is_hairpin)
continue;
MLX5_ASSERT(txq->idx == (uint16_t)i);
ret = txq_uar_init_secondary(txq_ctrl, fd);
txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
{
struct mlx5_priv *priv = txq_ctrl->priv;
- struct mlx5_dev_config *config = &priv->config;
+ struct mlx5_port_config *config = &priv->config;
struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;
unsigned int inlen_send; /* Inline data for ordinary SEND.*/
unsigned int inlen_empw; /* Inline data for enhanced MPW. */
txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
{
struct mlx5_priv *priv = txq_ctrl->priv;
- struct mlx5_dev_config *config = &priv->config;
+ struct mlx5_port_config *config = &priv->config;
unsigned int max_inline;
max_inline = txq_calc_inline_max(txq_ctrl);
goto error;
}
__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
- tmpl->type = MLX5_TXQ_TYPE_STANDARD;
+ tmpl->is_hairpin = false;
LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
return tmpl;
error:
tmpl->txq.port_id = dev->data->port_id;
tmpl->txq.idx = idx;
tmpl->hairpin_conf = *hairpin_conf;
- tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
+ tmpl->is_hairpin = true;
__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
return tmpl;
mlx5_free(txq_ctrl->obj);
txq_ctrl->obj = NULL;
}
- if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
+ if (!txq_ctrl->is_hairpin) {
if (txq_ctrl->txq.fcqs) {
mlx5_free(txq_ctrl->txq.fcqs);
txq_ctrl->txq.fcqs = NULL;
dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
}
if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) {
- if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
+ if (!txq_ctrl->is_hairpin)
mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh);
LIST_REMOVE(txq_ctrl, next);
mlx5_free(txq_ctrl);
int off, nbit;
unsigned int i;
uint64_t mask = 0;
+ uint64_t ts_mask;
+ if (sh->dev_cap.rt_timestamp ||
+ !sh->cdev->config.hca_attr.dev_freq_khz)
+ ts_mask = MLX5_TS_MASK_SECS << 32;
+ else
+ ts_mask = rte_align64pow2(MLX5_TS_MASK_SECS * 1000ull *
+ sh->cdev->config.hca_attr.dev_freq_khz);
+ ts_mask = rte_cpu_to_be_64(ts_mask - 1ull);
nbit = rte_mbuf_dynflag_lookup
(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
off = rte_mbuf_dynfield_lookup
(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL);
- if (nbit >= 0 && off >= 0 && sh->txpp.refcnt)
+ if (nbit >= 0 && off >= 0 &&
+ (sh->txpp.refcnt || priv->sh->cdev->config.hca_attr.wait_on_time))
mask = 1ULL << nbit;
for (i = 0; i != priv->txqs_n; ++i) {
data = (*priv->txqs)[i];
data->sh = sh;
data->ts_mask = mask;
data->ts_offset = off;
+ data->rt_timestamp = sh->dev_cap.rt_timestamp;
+ data->rt_timemask = (data->offloads &
+ RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) ?
+ ts_mask : 0;
}
}