net/mlx5: support descriptor LWM for Rx queue

[dpdk.git] / drivers / net / mlx5 / mlx5_txq.c

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 56e0937..0140f8b 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -100,34 +100,36 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
        struct mlx5_priv *priv = dev->data->dev_private;
        uint64_t offloads = (RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
                             RTE_ETH_TX_OFFLOAD_VLAN_INSERT);
-       struct mlx5_dev_config *config = &priv->config;
+       struct mlx5_port_config *config = &priv->config;
+       struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;
 
-       if (config->hw_csum)
+       if (dev_cap->hw_csum)
                offloads |= (RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
                             RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
                             RTE_ETH_TX_OFFLOAD_TCP_CKSUM);
-       if (config->tso)
+       if (dev_cap->tso)
                offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
-       if (config->tx_pp)
+       if (priv->sh->config.tx_pp ||
+           priv->sh->cdev->config.hca_attr.wait_on_time)
                offloads |= RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP;
-       if (config->swp) {
-               if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
+       if (dev_cap->swp) {
+               if (dev_cap->swp & MLX5_SW_PARSING_CSUM_CAP)
                        offloads |= RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-               if (config->swp & MLX5_SW_PARSING_TSO_CAP)
+               if (dev_cap->swp & MLX5_SW_PARSING_TSO_CAP)
                        offloads |= (RTE_ETH_TX_OFFLOAD_IP_TNL_TSO |
                                     RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO);
        }
-       if (config->tunnel_en) {
-               if (config->hw_csum)
+       if (dev_cap->tunnel_en) {
+               if (dev_cap->hw_csum)
                        offloads |= RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-               if (config->tso) {
-                       if (config->tunnel_en &
+               if (dev_cap->tso) {
+                       if (dev_cap->tunnel_en &
                                MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)
                                offloads |= RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO;
-                       if (config->tunnel_en &
+                       if (dev_cap->tunnel_en &
                                MLX5_TUNNELED_OFFLOADS_GRE_CAP)
                                offloads |= RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO;
-                       if (config->tunnel_en &
+                       if (dev_cap->tunnel_en &
                                MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)
                                offloads |= RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO;
                }
@@ -525,7 +527,7 @@ txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
                return -rte_errno;
        }
 
-       if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
+       if (txq_ctrl->is_hairpin)
                return 0;
        MLX5_ASSERT(ppriv);
        /*
@@ -568,7 +570,7 @@ txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
                rte_errno = ENOMEM;
        }
 
-       if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
+       if (txq_ctrl->is_hairpin)
                return;
        addr = ppriv->uar_table[txq_ctrl->txq.idx].db;
        rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
@@ -629,7 +631,7 @@ mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
                        continue;
                txq = (*priv->txqs)[i];
                txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
-               if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
+               if (txq_ctrl->is_hairpin)
                        continue;
                MLX5_ASSERT(txq->idx == (uint16_t)i);
                ret = txq_uar_init_secondary(txq_ctrl, fd);
@@ -740,7 +742,8 @@ static void
 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
 {
        struct mlx5_priv *priv = txq_ctrl->priv;
-       struct mlx5_dev_config *config = &priv->config;
+       struct mlx5_port_config *config = &priv->config;
+       struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;
        unsigned int inlen_send; /* Inline data for ordinary SEND.*/
        unsigned int inlen_empw; /* Inline data for enhanced MPW. */
        unsigned int inlen_mode; /* Minimal required Inline data. */
@@ -924,19 +927,19 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
                txq_ctrl->txq.tso_en = 1;
        }
        if (((RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&
-           (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
+           (dev_cap->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
           ((RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&
-           (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
+           (dev_cap->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
           ((RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&
-           (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
-          (config->swp  & MLX5_SW_PARSING_TSO_CAP))
+           (dev_cap->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
+          (dev_cap->swp  & MLX5_SW_PARSING_TSO_CAP))
                txq_ctrl->txq.tunnel_en = 1;
        txq_ctrl->txq.swp_en = (((RTE_ETH_TX_OFFLOAD_IP_TNL_TSO |
                                  RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO) &
-                                 txq_ctrl->txq.offloads) && (config->swp &
+                                 txq_ctrl->txq.offloads) && (dev_cap->swp &
                                  MLX5_SW_PARSING_TSO_CAP)) |
                                ((RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM &
-                                txq_ctrl->txq.offloads) && (config->swp &
+                                txq_ctrl->txq.offloads) && (dev_cap->swp &
                                 MLX5_SW_PARSING_CSUM_CAP));
 }
 
@@ -958,7 +961,7 @@ static int
 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
 {
        struct mlx5_priv *priv = txq_ctrl->priv;
-       struct mlx5_dev_config *config = &priv->config;
+       struct mlx5_port_config *config = &priv->config;
        unsigned int max_inline;
 
        max_inline = txq_calc_inline_max(txq_ctrl);
@@ -1104,7 +1107,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
                goto error;
        }
        __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
-       tmpl->type = MLX5_TXQ_TYPE_STANDARD;
+       tmpl->is_hairpin = false;
        LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
        return tmpl;
 error:
@@ -1147,7 +1150,7 @@ mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
        tmpl->txq.port_id = dev->data->port_id;
        tmpl->txq.idx = idx;
        tmpl->hairpin_conf = *hairpin_conf;
-       tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
+       tmpl->is_hairpin = true;
        __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
        LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
        return tmpl;
@@ -1206,7 +1209,7 @@ mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
                mlx5_free(txq_ctrl->obj);
                txq_ctrl->obj = NULL;
        }
-       if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD) {
+       if (!txq_ctrl->is_hairpin) {
                if (txq_ctrl->txq.fcqs) {
                        mlx5_free(txq_ctrl->txq.fcqs);
                        txq_ctrl->txq.fcqs = NULL;
@@ -1215,7 +1218,7 @@ mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
                dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
        }
        if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) {
-               if (txq_ctrl->type == MLX5_TXQ_TYPE_STANDARD)
+               if (!txq_ctrl->is_hairpin)
                        mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh);
                LIST_REMOVE(txq_ctrl, next);
                mlx5_free(txq_ctrl);
@@ -1286,12 +1289,21 @@ mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev)
        int off, nbit;
        unsigned int i;
        uint64_t mask = 0;
+       uint64_t ts_mask;
 
+       if (sh->dev_cap.rt_timestamp ||
+           !sh->cdev->config.hca_attr.dev_freq_khz)
+               ts_mask = MLX5_TS_MASK_SECS << 32;
+       else
+               ts_mask = rte_align64pow2(MLX5_TS_MASK_SECS * 1000ull *
+                               sh->cdev->config.hca_attr.dev_freq_khz);
+       ts_mask = rte_cpu_to_be_64(ts_mask - 1ull);
        nbit = rte_mbuf_dynflag_lookup
                                (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
        off = rte_mbuf_dynfield_lookup
                                (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL);
-       if (nbit >= 0 && off >= 0 && sh->txpp.refcnt)
+       if (nbit >= 0 && off >= 0 &&
+           (sh->txpp.refcnt || priv->sh->cdev->config.hca_attr.wait_on_time))
                mask = 1ULL << nbit;
        for (i = 0; i != priv->txqs_n; ++i) {
                data = (*priv->txqs)[i];
@@ -1300,5 +1312,9 @@ mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev)
                data->sh = sh;
                data->ts_mask = mask;
                data->ts_offset = off;
+               data->rt_timestamp = sh->dev_cap.rt_timestamp;
+               data->rt_timemask = (data->offloads &
+                                    RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) ?
+                                    ts_mask : 0;
        }
 }