net/mlx5: fix setting of port ID for egress rules

[dpdk.git] / drivers / net / mlx5 / mlx5_txq.c

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 5e45748..1a76f6e 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -62,7 +62,7 @@ txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
  * @param txq_ctrl
  *   Pointer to TX queue structure.
  */
-static void
+void
 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
 {
        const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
@@ -127,7 +127,8 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
                        offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
                if (config->tso)
                        offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
-                                    DEV_TX_OFFLOAD_GRE_TNL_TSO);
+                                    DEV_TX_OFFLOAD_GRE_TNL_TSO |
+                                    DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
        }
        return offloads;
 }
@@ -271,7 +272,6 @@ mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
        DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
                dev->data->port_id, idx);
        (*priv->txqs)[idx] = &txq_ctrl->txq;
-       txq_ctrl->type = MLX5_TXQ_TYPE_HAIRPIN;
        return 0;
 }
 
@@ -314,7 +314,7 @@ static void
 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
 {
        struct mlx5_priv *priv = txq_ctrl->priv;
-       unsigned int cmd;
+       off_t cmd;
 
        txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
        txq_ctrl->txq.db_nc = 0;
@@ -717,13 +717,22 @@ mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
        txq_data->cq_db = cq_info.dbrec;
        txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
        txq_data->cq_ci = 0;
-#ifndef NDEBUG
        txq_data->cq_pi = 0;
-#endif
        txq_data->wqe_ci = 0;
        txq_data->wqe_pi = 0;
        txq_data->wqe_comp = 0;
        txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
+       txq_data->fcqs = rte_calloc_socket(__func__,
+                                          txq_data->cqe_s,
+                                          sizeof(*txq_data->fcqs),
+                                          RTE_CACHE_LINE_SIZE,
+                                          txq_ctrl->socket);
+       if (!txq_data->fcqs) {
+               DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
+                       dev->data->port_id, idx);
+               rte_errno = ENOMEM;
+               goto error;
+       }
 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
        /*
         * If using DevX need to query and store TIS transport domain value.
@@ -772,6 +781,8 @@ error:
                claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
        if (tmpl.qp)
                claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
+       if (txq_data && txq_data->fcqs)
+               rte_free(txq_data->fcqs);
        if (txq_obj)
                rte_free(txq_obj);
        priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
@@ -826,6 +837,8 @@ mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)
                } else {
                        claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
                        claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
+                               if (txq_obj->txq_ctrl->txq.fcqs)
+                                       rte_free(txq_obj->txq_ctrl->txq.fcqs);
                }
                LIST_REMOVE(txq_obj, next);
                rte_free(txq_obj);