net/bnxt: enhance RSS action support

[dpdk.git] / drivers / net / mlx5 / mlx5_txq.c

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index eb4d34c..1f92250 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -111,19 +111,26 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
        if (config->tx_pp)
                offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
        if (config->swp) {
-               if (config->hw_csum)
+               if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
                        offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-               if (config->tso)
+               if (config->swp & MLX5_SW_PARSING_TSO_CAP)
                        offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
                                     DEV_TX_OFFLOAD_UDP_TNL_TSO);
        }
        if (config->tunnel_en) {
                if (config->hw_csum)
                        offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-               if (config->tso)
-                       offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
-                                    DEV_TX_OFFLOAD_GRE_TNL_TSO |
-                                    DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
+               if (config->tso) {
+                       if (config->tunnel_en &
+                               MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)
+                               offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
+                       if (config->tunnel_en &
+                               MLX5_TUNNELED_OFFLOADS_GRE_CAP)
+                               offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO;
+                       if (config->tunnel_en &
+                               MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)
+                               offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
+               }
        }
        if (!config->mprq.enabled)
                offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
@@ -470,28 +477,21 @@ mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 /**
  * DPDK callback to release a TX queue.
  *
- * @param dpdk_txq
- *   Generic TX queue pointer.
+ * @param dev
+ *   Pointer to Ethernet device structure.
+ * @param qid
+ *   Transmit queue index.
  */
 void
-mlx5_tx_queue_release(void *dpdk_txq)
+mlx5_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 {
-       struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
-       struct mlx5_txq_ctrl *txq_ctrl;
-       struct mlx5_priv *priv;
-       unsigned int i;
+       struct mlx5_txq_data *txq = dev->data->tx_queues[qid];
 
        if (txq == NULL)
                return;
-       txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
-       priv = txq_ctrl->priv;
-       for (i = 0; (i != priv->txqs_n); ++i)
-               if ((*priv->txqs)[i] == txq) {
-                       DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
-                               PORT_ID(priv), txq->idx);
-                       mlx5_txq_release(ETH_DEV(priv), i);
-                       break;
-               }
+       DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
+               dev->data->port_id, qid);
+       mlx5_txq_release(dev, qid);
 }
 
 /**
@@ -978,11 +978,21 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
                                                    MLX5_MAX_TSO_HEADER);
                txq_ctrl->txq.tso_en = 1;
        }
-       txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
-       txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
-                                DEV_TX_OFFLOAD_UDP_TNL_TSO |
-                                DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
-                               txq_ctrl->txq.offloads) && config->swp;
+       if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&
+           (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
+          ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&
+           (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
+          ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&
+           (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
+          (config->swp  & MLX5_SW_PARSING_TSO_CAP))
+               txq_ctrl->txq.tunnel_en = 1;
+       txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
+                                 DEV_TX_OFFLOAD_UDP_TNL_TSO) &
+                                 txq_ctrl->txq.offloads) && (config->swp &
+                                 MLX5_SW_PARSING_TSO_CAP)) |
+                               ((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
+                                txq_ctrl->txq.offloads) && (config->swp &
+                                MLX5_SW_PARSING_CSUM_CAP));
 }
 
 /**