net/mlx5: replace countdown with threshold for Tx completions

[dpdk.git] / drivers / net / mlx5 / mlx5_txq.c

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 22e9bae..7b2dc7c 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -89,6 +89,7 @@ txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)
        DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
        txq_ctrl->txq.elts_head = 0;
        txq_ctrl->txq.elts_tail = 0;
+       txq_ctrl->txq.elts_comp = 0;
 }
 
 /**
@@ -108,6 +109,7 @@ txq_free_elts(struct txq_ctrl *txq_ctrl)
        DEBUG("%p: freeing WRs", (void *)txq_ctrl);
        txq_ctrl->txq.elts_head = 0;
        txq_ctrl->txq.elts_tail = 0;
+       txq_ctrl->txq.elts_comp = 0;
 
        while (elts_tail != elts_head) {
                struct rte_mbuf *elt = (*elts)[elts_tail];
@@ -274,15 +276,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
                goto error;
        }
        (void)conf; /* Thresholds configuration (ignored). */
+       assert(desc > MLX5_TX_COMP_THRESH);
        tmpl.txq.elts_n = desc;
-       /*
-        * Request send completion every MLX5_PMD_TX_PER_COMP_REQ packets or
-        * at least 4 times per ring.
-        */
-       tmpl.txq.elts_comp_cd_init =
-               ((MLX5_PMD_TX_PER_COMP_REQ < (desc / 4)) ?
-                MLX5_PMD_TX_PER_COMP_REQ : (desc / 4));
-       tmpl.txq.elts_comp = tmpl.txq.elts_comp_cd_init;
        /* MRs will be registered in mp2mr[] later. */
        attr.rd = (struct ibv_exp_res_domain_init_attr){
                .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
@@ -302,7 +297,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,
                .res_domain = tmpl.rd,
        };
        tmpl.cq = ibv_exp_create_cq(priv->ctx,
-                                   (desc / tmpl.txq.elts_comp_cd_init) - 1,
+                                   (((desc / MLX5_TX_COMP_THRESH) - 1) ?
+                                    ((desc / MLX5_TX_COMP_THRESH) - 1) : 1),
                                    NULL, NULL, 0, &attr.cq);
        if (tmpl.cq == NULL) {
                ret = ENOMEM;
@@ -454,6 +450,13 @@ mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
                return -E_RTE_SECONDARY;
 
        priv_lock(priv);
+       if (desc <= MLX5_TX_COMP_THRESH) {
+               WARN("%p: number of descriptors requested for TX queue %u"
+                    " must be higher than MLX5_TX_COMP_THRESH, using"
+                    " %u instead of %u",
+                    (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
+               desc = MLX5_TX_COMP_THRESH + 1;
+       }
        if (!rte_is_power_of_2(desc)) {
                desc = 1 << log2above(desc);
                WARN("%p: increased number of descriptors in TX queue %u"