#include <mlx5_devx_cmds.h>
#include <mlx5_common.h>
#include <mlx5_common_mr.h>
-#include <mlx5_common_os.h>
#include <mlx5_malloc.h>
#include "mlx5_defs.h"
cqe->op_own = MLX5_CQE_INVALIDATE;
}
/* Resync CQE and WQE (WQ in reset state). */
- rte_cio_wmb();
+ rte_io_wmb();
*txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
- rte_cio_wmb();
+ rte_io_wmb();
}
/**
{
int ret;
- if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
+ if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) {
DRV_LOG(ERR, "Hairpin queue can't be stopped");
rte_errno = EINVAL;
return -EINVAL;
{
int ret;
- if (dev->data->tx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
+ if (rte_eth_dev_is_tx_hairpin_queue(dev, idx)) {
DRV_LOG(ERR, "Hairpin queue can't be started");
rte_errno = EINVAL;
return -EINVAL;
mlx5_txq_release(dev, idx);
return 0;
}
+
/**
* DPDK callback to configure a TX queue.
*
* @param txq_ctrl
* Pointer to Tx queue control structure.
*/
-static void
+void
txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
{
struct mlx5_priv *priv = txq_ctrl->priv;
return -rte_errno;
}
-/**
- * Create the Tx hairpin queue object.
- *
- * @param dev
- * Pointer to Ethernet device.
- * @param idx
- * Queue index in DPDK Tx queue array
- *
- * @return
- * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
- */
-static struct mlx5_txq_obj *
-mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
-{
- struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
- struct mlx5_txq_ctrl *txq_ctrl =
- container_of(txq_data, struct mlx5_txq_ctrl, txq);
- struct mlx5_devx_create_sq_attr attr = { 0 };
- struct mlx5_txq_obj *tmpl = NULL;
- uint32_t max_wq_data;
-
- MLX5_ASSERT(txq_data);
- MLX5_ASSERT(!txq_ctrl->obj);
- tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
- txq_ctrl->socket);
- if (!tmpl) {
- DRV_LOG(ERR,
- "port %u Tx queue %u cannot allocate memory resources",
- dev->data->port_id, txq_data->idx);
- rte_errno = ENOMEM;
- return NULL;
- }
- tmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;
- tmpl->txq_ctrl = txq_ctrl;
- attr.hairpin = 1;
- attr.tis_lst_sz = 1;
- max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
- /* Jumbo frames > 9KB should be supported, and more packets. */
- if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
- if (priv->config.log_hp_size > max_wq_data) {
- DRV_LOG(ERR, "total data size %u power of 2 is "
- "too large for hairpin",
- priv->config.log_hp_size);
- mlx5_free(tmpl);
- rte_errno = ERANGE;
- return NULL;
- }
- attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
- } else {
- attr.wq_attr.log_hairpin_data_sz =
- (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
- max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
- }
- /* Set the packets number to the maximum value for performance. */
- attr.wq_attr.log_hairpin_num_packets =
- attr.wq_attr.log_hairpin_data_sz -
- MLX5_HAIRPIN_QUEUE_STRIDE;
- attr.tis_num = priv->sh->tis->id;
- tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
- if (!tmpl->sq) {
- DRV_LOG(ERR,
- "port %u tx hairpin queue %u can't create sq object",
- dev->data->port_id, idx);
- mlx5_free(tmpl);
- rte_errno = errno;
- return NULL;
- }
- DRV_LOG(DEBUG, "port %u sxq %u updated with %p", dev->data->port_id,
- idx, (void *)&tmpl);
- rte_atomic32_inc(&tmpl->refcnt);
- LIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);
- return tmpl;
-}
-
-/**
- * Destroy the Tx queue DevX object.
- *
- * @param txq_obj
- * Txq object to destroy
- */
-static void
-txq_release_sq_resources(struct mlx5_txq_obj *txq_obj)
-{
- MLX5_ASSERT(txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ);
-
- if (txq_obj->sq_devx)
- claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq_devx));
- if (txq_obj->sq_dbrec_page)
- claim_zero(mlx5_release_dbr
- (&txq_obj->txq_ctrl->priv->dbrpgs,
- mlx5_os_get_umem_id
- (txq_obj->sq_dbrec_page->umem),
- txq_obj->sq_dbrec_offset));
- if (txq_obj->sq_umem)
- claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->sq_umem));
- if (txq_obj->sq_buf)
- mlx5_free(txq_obj->sq_buf);
- if (txq_obj->cq_devx)
- claim_zero(mlx5_devx_cmd_destroy(txq_obj->cq_devx));
- if (txq_obj->cq_dbrec_page)
- claim_zero(mlx5_release_dbr
- (&txq_obj->txq_ctrl->priv->dbrpgs,
- mlx5_os_get_umem_id
- (txq_obj->cq_dbrec_page->umem),
- txq_obj->cq_dbrec_offset));
- if (txq_obj->cq_umem)
- claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->cq_umem));
- if (txq_obj->cq_buf)
- mlx5_free(txq_obj->cq_buf);
-}
-
-/**
- * Create the Tx queue DevX object.
- *
- * @param dev
- * Pointer to Ethernet device.
- * @param idx
- * Queue index in DPDK Tx queue array
- *
- * @return
- * The DevX object initialised, NULL otherwise and rte_errno is set.
- */
-static struct mlx5_txq_obj *
-mlx5_txq_obj_devx_new(struct rte_eth_dev *dev, uint16_t idx)
-{
-#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
- DRV_LOG(ERR, "port %u Tx queue %u cannot create with DevX, no UAR",
- dev->data->port_id, idx);
- rte_errno = ENOMEM;
- return NULL;
-#else
- struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_dev_ctx_shared *sh = priv->sh;
- struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
- struct mlx5_txq_ctrl *txq_ctrl =
- container_of(txq_data, struct mlx5_txq_ctrl, txq);
- struct mlx5_devx_create_sq_attr sq_attr = { 0 };
- struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
- struct mlx5_devx_cq_attr cq_attr = { 0 };
- struct mlx5_txq_obj *txq_obj = NULL;
- size_t page_size;
- struct mlx5_cqe *cqe;
- uint32_t i, nqe;
- void *reg_addr;
- size_t alignment = (size_t)-1;
- int ret = 0;
-
- MLX5_ASSERT(txq_data);
- MLX5_ASSERT(!txq_ctrl->obj);
- page_size = rte_mem_page_size();
- if (page_size == (size_t)-1) {
- DRV_LOG(ERR, "Failed to get mem page size");
- rte_errno = ENOMEM;
- return NULL;
- }
- txq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
- sizeof(struct mlx5_txq_obj), 0,
- txq_ctrl->socket);
- if (!txq_obj) {
- DRV_LOG(ERR,
- "port %u Tx queue %u cannot allocate memory resources",
- dev->data->port_id, txq_data->idx);
- rte_errno = ENOMEM;
- return NULL;
- }
- txq_obj->type = MLX5_TXQ_OBJ_TYPE_DEVX_SQ;
- txq_obj->txq_ctrl = txq_ctrl;
- txq_obj->dev = dev;
- /* Create the Completion Queue. */
- nqe = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
- 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
- nqe = 1UL << log2above(nqe);
- if (nqe > UINT16_MAX) {
- DRV_LOG(ERR,
- "port %u Tx queue %u requests to many CQEs %u",
- dev->data->port_id, txq_data->idx, nqe);
- rte_errno = EINVAL;
- goto error;
- }
- /* Allocate memory buffer for CQEs. */
- alignment = MLX5_CQE_BUF_ALIGNMENT;
- if (alignment == (size_t)-1) {
- DRV_LOG(ERR, "Failed to get mem page size");
- rte_errno = ENOMEM;
- goto error;
- }
- txq_obj->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
- nqe * sizeof(struct mlx5_cqe),
- alignment,
- sh->numa_node);
- if (!txq_obj->cq_buf) {
- DRV_LOG(ERR,
- "port %u Tx queue %u cannot allocate memory (CQ)",
- dev->data->port_id, txq_data->idx);
- rte_errno = ENOMEM;
- goto error;
- }
- txq_data->cqe_n = log2above(nqe);
- txq_data->cqe_s = 1 << txq_data->cqe_n;
- txq_data->cqe_m = txq_data->cqe_s - 1;
- txq_data->cqes = (volatile struct mlx5_cqe *)txq_obj->cq_buf;
- txq_data->cq_ci = 0;
- txq_data->cq_pi = 0;
- /* Register allocated buffer in user space with DevX. */
- txq_obj->cq_umem = mlx5_glue->devx_umem_reg
- (sh->ctx,
- (void *)txq_obj->cq_buf,
- nqe * sizeof(struct mlx5_cqe),
- IBV_ACCESS_LOCAL_WRITE);
- if (!txq_obj->cq_umem) {
- rte_errno = errno;
- DRV_LOG(ERR,
- "port %u Tx queue %u cannot register memory (CQ)",
- dev->data->port_id, txq_data->idx);
- goto error;
- }
- /* Allocate doorbell record for completion queue. */
- txq_obj->cq_dbrec_offset = mlx5_get_dbr(sh->ctx,
- &priv->dbrpgs,
- &txq_obj->cq_dbrec_page);
- if (txq_obj->cq_dbrec_offset < 0)
- goto error;
- txq_data->cq_db = (volatile uint32_t *)(txq_obj->cq_dbrec_page->dbrs +
- txq_obj->cq_dbrec_offset);
- *txq_data->cq_db = 0;
- /* Create completion queue object with DevX. */
- cq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?
- MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;
- cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
- cq_attr.eqn = sh->txpp.eqn;
- cq_attr.q_umem_valid = 1;
- cq_attr.q_umem_offset = (uintptr_t)txq_obj->cq_buf % page_size;
- cq_attr.q_umem_id = mlx5_os_get_umem_id(txq_obj->cq_umem);
- cq_attr.db_umem_valid = 1;
- cq_attr.db_umem_offset = txq_obj->cq_dbrec_offset;
- cq_attr.db_umem_id = mlx5_os_get_umem_id(txq_obj->cq_dbrec_page->umem);
- cq_attr.log_cq_size = rte_log2_u32(nqe);
- cq_attr.log_page_size = rte_log2_u32(page_size);
- txq_obj->cq_devx = mlx5_devx_cmd_create_cq(sh->ctx, &cq_attr);
- if (!txq_obj->cq_devx) {
- rte_errno = errno;
- DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
- dev->data->port_id, idx);
- goto error;
- }
- /* Initial fill CQ buffer with invalid CQE opcode. */
- cqe = (struct mlx5_cqe *)txq_obj->cq_buf;
- for (i = 0; i < txq_data->cqe_s; i++) {
- cqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;
- ++cqe;
- }
- /* Create the Work Queue. */
- nqe = RTE_MIN(1UL << txq_data->elts_n,
- (uint32_t)sh->device_attr.max_qp_wr);
- txq_obj->sq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
- nqe * sizeof(struct mlx5_wqe),
- page_size, sh->numa_node);
- if (!txq_obj->sq_buf) {
- DRV_LOG(ERR,
- "port %u Tx queue %u cannot allocate memory (SQ)",
- dev->data->port_id, txq_data->idx);
- rte_errno = ENOMEM;
- goto error;
- }
- txq_data->wqe_n = log2above(nqe);
- txq_data->wqe_s = 1 << txq_data->wqe_n;
- txq_data->wqe_m = txq_data->wqe_s - 1;
- txq_data->wqes = (struct mlx5_wqe *)txq_obj->sq_buf;
- txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
- txq_data->wqe_ci = 0;
- txq_data->wqe_pi = 0;
- txq_data->wqe_comp = 0;
- txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
- /* Register allocated buffer in user space with DevX. */
- txq_obj->sq_umem = mlx5_glue->devx_umem_reg
- (sh->ctx,
- (void *)txq_obj->sq_buf,
- nqe * sizeof(struct mlx5_wqe),
- IBV_ACCESS_LOCAL_WRITE);
- if (!txq_obj->sq_umem) {
- rte_errno = errno;
- DRV_LOG(ERR,
- "port %u Tx queue %u cannot register memory (SQ)",
- dev->data->port_id, txq_data->idx);
- goto error;
- }
- /* Allocate doorbell record for completion queue. */
- txq_obj->cq_dbrec_offset = mlx5_get_dbr(sh->ctx,
- &priv->dbrpgs,
- &txq_obj->sq_dbrec_page);
- if (txq_obj->sq_dbrec_offset < 0)
- goto error;
- txq_data->qp_db = (volatile uint32_t *)
- (txq_obj->sq_dbrec_page->dbrs +
- txq_obj->sq_dbrec_offset +
- MLX5_SND_DBR * sizeof(uint32_t));
- *txq_data->qp_db = 0;
- /* Create Send Queue object with DevX. */
- sq_attr.tis_lst_sz = 1;
- sq_attr.tis_num = sh->tis->id;
- sq_attr.state = MLX5_SQC_STATE_RST;
- sq_attr.cqn = txq_obj->cq_devx->id;
- sq_attr.flush_in_error_en = 1;
- sq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;
- sq_attr.allow_swp = !!priv->config.swp;
- sq_attr.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode;
- sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
- sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
- sq_attr.wq_attr.pd = sh->pdn;
- sq_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);
- sq_attr.wq_attr.log_wq_sz = txq_data->wqe_n;
- sq_attr.wq_attr.dbr_umem_valid = 1;
- sq_attr.wq_attr.dbr_addr = txq_obj->cq_dbrec_offset;
- sq_attr.wq_attr.dbr_umem_id =
- mlx5_os_get_umem_id(txq_obj->cq_dbrec_page->umem);
- sq_attr.wq_attr.wq_umem_valid = 1;
- sq_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(txq_obj->sq_umem);
- sq_attr.wq_attr.wq_umem_offset = (uintptr_t)txq_obj->sq_buf % page_size;
- txq_obj->sq_devx = mlx5_devx_cmd_create_sq(sh->ctx, &sq_attr);
- if (!txq_obj->sq_devx) {
- rte_errno = errno;
- DRV_LOG(ERR, "port %u Tx queue %u SQ creation failure",
- dev->data->port_id, idx);
- goto error;
- }
- txq_data->qp_num_8s = txq_obj->sq_devx->id << 8;
- /* Change Send Queue state to Ready-to-Send. */
- msq_attr.sq_state = MLX5_SQC_STATE_RST;
- msq_attr.state = MLX5_SQC_STATE_RDY;
- ret = mlx5_devx_cmd_modify_sq(txq_obj->sq_devx, &msq_attr);
- if (ret) {
- rte_errno = errno;
- DRV_LOG(ERR,
- "port %u Tx queue %u SP state to SQC_STATE_RDY failed",
- dev->data->port_id, idx);
- goto error;
- }
- txq_data->fcqs = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
- txq_data->cqe_s * sizeof(*txq_data->fcqs),
- RTE_CACHE_LINE_SIZE,
- txq_ctrl->socket);
- if (!txq_data->fcqs) {
- DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
- dev->data->port_id, idx);
- rte_errno = ENOMEM;
- goto error;
- }
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- /*
- * If using DevX need to query and store TIS transport domain value.
- * This is done once per port.
- * Will use this value on Rx, when creating matching TIR.
- */
- if (priv->config.devx && !priv->sh->tdn)
- priv->sh->tdn = priv->sh->td->id;
-#endif
- MLX5_ASSERT(sh->tx_uar);
- reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
- MLX5_ASSERT(reg_addr);
- txq_ctrl->bf_reg = reg_addr;
- txq_ctrl->uar_mmap_offset =
- mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);
- rte_atomic32_set(&txq_obj->refcnt, 1);
- txq_uar_init(txq_ctrl);
- LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
- return txq_obj;
-error:
- ret = rte_errno; /* Save rte_errno before cleanup. */
- txq_release_sq_resources(txq_obj);
- if (txq_data->fcqs) {
- mlx5_free(txq_data->fcqs);
- txq_data->fcqs = NULL;
- }
- mlx5_free(txq_obj);
- rte_errno = ret; /* Restore rte_errno. */
- return NULL;
-#endif
-}
-
-/**
- * Create the Tx queue Verbs object.
- *
- * @param dev
- * Pointer to Ethernet device.
- * @param idx
- * Queue index in DPDK Tx queue array.
- * @param type
- * Type of the Tx queue object to create.
- *
- * @return
- * The Verbs object initialised, NULL otherwise and rte_errno is set.
- */
-struct mlx5_txq_obj *
-mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
- enum mlx5_txq_obj_type type)
-{
- struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
- struct mlx5_txq_ctrl *txq_ctrl =
- container_of(txq_data, struct mlx5_txq_ctrl, txq);
- struct mlx5_txq_obj tmpl;
- struct mlx5_txq_obj *txq_obj = NULL;
- union {
- struct ibv_qp_init_attr_ex init;
- struct ibv_cq_init_attr_ex cq;
- struct ibv_qp_attr mod;
- } attr;
- unsigned int cqe_n;
- struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
- struct mlx5dv_cq cq_info;
- struct mlx5dv_obj obj;
- const int desc = 1 << txq_data->elts_n;
- int ret = 0;
-
- if (type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN)
- return mlx5_txq_obj_hairpin_new(dev, idx);
- if (type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ)
- return mlx5_txq_obj_devx_new(dev, idx);
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- /* If using DevX, need additional mask to read tisn value. */
- if (priv->config.devx && !priv->sh->tdn)
- qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
-#endif
- MLX5_ASSERT(txq_data);
- priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
- priv->verbs_alloc_ctx.obj = txq_ctrl;
- if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
- DRV_LOG(ERR,
- "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
- dev->data->port_id);
- rte_errno = EINVAL;
- return NULL;
- }
- memset(&tmpl, 0, sizeof(struct mlx5_txq_obj));
- attr.cq = (struct ibv_cq_init_attr_ex){
- .comp_mask = 0,
- };
- cqe_n = desc / MLX5_TX_COMP_THRESH +
- 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
- tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
- if (tmpl.cq == NULL) {
- DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
- dev->data->port_id, idx);
- rte_errno = errno;
- goto error;
- }
- attr.init = (struct ibv_qp_init_attr_ex){
- /* CQ to be associated with the send queue. */
- .send_cq = tmpl.cq,
- /* CQ to be associated with the receive queue. */
- .recv_cq = tmpl.cq,
- .cap = {
- /* Max number of outstanding WRs. */
- .max_send_wr =
- ((priv->sh->device_attr.max_qp_wr <
- desc) ?
- priv->sh->device_attr.max_qp_wr :
- desc),
- /*
- * Max number of scatter/gather elements in a WR,
- * must be 1 to prevent libmlx5 from trying to affect
- * too much memory. TX gather is not impacted by the
- * device_attr.max_sge limit and will still work
- * properly.
- */
- .max_send_sge = 1,
- },
- .qp_type = IBV_QPT_RAW_PACKET,
- /*
- * Do *NOT* enable this, completions events are managed per
- * Tx burst.
- */
- .sq_sig_all = 0,
- .pd = priv->sh->pd,
- .comp_mask = IBV_QP_INIT_ATTR_PD,
- };
- if (txq_data->inlen_send)
- attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
- if (txq_data->tso_en) {
- attr.init.max_tso_header = txq_ctrl->max_tso_header;
- attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
- }
- tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
- if (tmpl.qp == NULL) {
- DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
- dev->data->port_id, idx);
- rte_errno = errno;
- goto error;
- }
- attr.mod = (struct ibv_qp_attr){
- /* Move the QP to this state. */
- .qp_state = IBV_QPS_INIT,
- /* IB device port number. */
- .port_num = (uint8_t)priv->dev_port,
- };
- ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
- (IBV_QP_STATE | IBV_QP_PORT));
- if (ret) {
- DRV_LOG(ERR,
- "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
- dev->data->port_id, idx);
- rte_errno = errno;
- goto error;
- }
- attr.mod = (struct ibv_qp_attr){
- .qp_state = IBV_QPS_RTR
- };
- ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
- if (ret) {
- DRV_LOG(ERR,
- "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
- dev->data->port_id, idx);
- rte_errno = errno;
- goto error;
- }
- attr.mod.qp_state = IBV_QPS_RTS;
- ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
- if (ret) {
- DRV_LOG(ERR,
- "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
- dev->data->port_id, idx);
- rte_errno = errno;
- goto error;
- }
- txq_obj = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
- sizeof(struct mlx5_txq_obj), 0,
- txq_ctrl->socket);
- if (!txq_obj) {
- DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
- dev->data->port_id, idx);
- rte_errno = ENOMEM;
- goto error;
- }
- obj.cq.in = tmpl.cq;
- obj.cq.out = &cq_info;
- obj.qp.in = tmpl.qp;
- obj.qp.out = &qp;
- ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
- if (ret != 0) {
- rte_errno = errno;
- goto error;
- }
- if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
- DRV_LOG(ERR,
- "port %u wrong MLX5_CQE_SIZE environment variable"
- " value: it should be set to %u",
- dev->data->port_id, RTE_CACHE_LINE_SIZE);
- rte_errno = EINVAL;
- goto error;
- }
- txq_data->cqe_n = log2above(cq_info.cqe_cnt);
- txq_data->cqe_s = 1 << txq_data->cqe_n;
- txq_data->cqe_m = txq_data->cqe_s - 1;
- txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
- txq_data->wqes = qp.sq.buf;
- txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
- txq_data->wqe_s = 1 << txq_data->wqe_n;
- txq_data->wqe_m = txq_data->wqe_s - 1;
- txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
- txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
- txq_data->cq_db = cq_info.dbrec;
- txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
- txq_data->cq_ci = 0;
- txq_data->cq_pi = 0;
- txq_data->wqe_ci = 0;
- txq_data->wqe_pi = 0;
- txq_data->wqe_comp = 0;
- txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
- txq_data->fcqs = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
- txq_data->cqe_s * sizeof(*txq_data->fcqs),
- RTE_CACHE_LINE_SIZE, txq_ctrl->socket);
- if (!txq_data->fcqs) {
- DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
- dev->data->port_id, idx);
- rte_errno = ENOMEM;
- goto error;
- }
-#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- /*
- * If using DevX need to query and store TIS transport domain value.
- * This is done once per port.
- * Will use this value on Rx, when creating matching TIR.
- */
- if (priv->config.devx && !priv->sh->tdn) {
- ret = mlx5_devx_cmd_qp_query_tis_td(tmpl.qp, qp.tisn,
- &priv->sh->tdn);
- if (ret) {
- DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
- "transport domain", dev->data->port_id, idx);
- rte_errno = EINVAL;
- goto error;
- } else {
- DRV_LOG(DEBUG, "port %u Tx queue %u TIS number %d "
- "transport domain %d", dev->data->port_id,
- idx, qp.tisn, priv->sh->tdn);
- }
- }
-#endif
- txq_obj->qp = tmpl.qp;
- txq_obj->cq = tmpl.cq;
- rte_atomic32_inc(&txq_obj->refcnt);
- txq_ctrl->bf_reg = qp.bf.reg;
- if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
- txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
- DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
- dev->data->port_id, txq_ctrl->uar_mmap_offset);
- } else {
- DRV_LOG(ERR,
- "port %u failed to retrieve UAR info, invalid"
- " libmlx5.so",
- dev->data->port_id);
- rte_errno = EINVAL;
- goto error;
- }
- txq_uar_init(txq_ctrl);
- LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
- txq_obj->txq_ctrl = txq_ctrl;
- priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
- return txq_obj;
-error:
- ret = rte_errno; /* Save rte_errno before cleanup. */
- if (tmpl.cq)
- claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
- if (tmpl.qp)
- claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
- if (txq_data && txq_data->fcqs) {
- mlx5_free(txq_data->fcqs);
- txq_data->fcqs = NULL;
- }
- if (txq_obj)
- mlx5_free(txq_obj);
- priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
- rte_errno = ret; /* Restore rte_errno. */
- return NULL;
-}
-
-/**
- * Get an Tx queue Verbs object.
- *
- * @param dev
- * Pointer to Ethernet device.
- * @param idx
- * Queue index in DPDK Tx queue array.
- *
- * @return
- * The Verbs object if it exists.
- */
-struct mlx5_txq_obj *
-mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
-{
- struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_txq_ctrl *txq_ctrl;
-
- if (idx >= priv->txqs_n)
- return NULL;
- if (!(*priv->txqs)[idx])
- return NULL;
- txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
- if (txq_ctrl->obj)
- rte_atomic32_inc(&txq_ctrl->obj->refcnt);
- return txq_ctrl->obj;
-}
-
-/**
- * Release an Tx verbs queue object.
- *
- * @param txq_obj
- * Verbs Tx queue object.
- *
- * @return
- * 1 while a reference on it exists, 0 when freed.
- */
-int
-mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)
-{
- MLX5_ASSERT(txq_obj);
- if (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {
- if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {
- if (txq_obj->tis)
- claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
- } else if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ) {
- txq_release_sq_resources(txq_obj);
- } else {
- claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
- claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
- }
- if (txq_obj->txq_ctrl->txq.fcqs) {
- mlx5_free(txq_obj->txq_ctrl->txq.fcqs);
- txq_obj->txq_ctrl->txq.fcqs = NULL;
- }
- LIST_REMOVE(txq_obj, next);
- mlx5_free(txq_obj);
- return 0;
- }
- return 1;
-}
-
/**
* Verify the Verbs Tx queue list is empty
*
mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
{
struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
struct mlx5_txq_ctrl *ctrl = NULL;
- if ((*priv->txqs)[idx]) {
- ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
- txq);
- mlx5_txq_obj_get(dev, idx);
+ if (txq_data) {
+ ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq);
rte_atomic32_inc(&ctrl->refcnt);
}
return ctrl;
if (!(*priv->txqs)[idx])
return 0;
txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
- if (txq->obj && !mlx5_txq_obj_release(txq->obj))
+ if (!rte_atomic32_dec_and_test(&txq->refcnt))
+ return 1;
+ if (txq->obj) {
+ priv->obj_ops.txq_obj_release(txq->obj);
txq->obj = NULL;
- if (rte_atomic32_dec_and_test(&txq->refcnt)) {
- txq_free_elts(txq);
- mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
- LIST_REMOVE(txq, next);
- mlx5_free(txq);
- (*priv->txqs)[idx] = NULL;
- dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
- return 0;
}
- return 1;
+ txq_free_elts(txq);
+ mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
+ LIST_REMOVE(txq, next);
+ mlx5_free(txq);
+ (*priv->txqs)[idx] = NULL;
+ dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
+ return 0;
}
/**
git.droids-corp.org / dpdk.git / blobdiff