-/*-
- * BSD LICENSE
- *
- * Copyright(c) 2017 Marvell International Ltd.
- * Copyright(c) 2017 Semihalf.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Semihalf nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Marvell International Ltd.
+ * Copyright(c) 2017 Semihalf.
+ * All rights reserved.
*/
-#include <rte_ethdev.h>
+#include <rte_ethdev_driver.h>
#include <rte_kvargs.h>
#include <rte_log.h>
#include <rte_malloc.h>
/* Memory size (in bytes) for MUSDK dma buffers */
#define MRVL_MUSDK_DMA_MEMSIZE 41943040
+/** Port Rx offload capabilities */
+#define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
+ DEV_RX_OFFLOAD_JUMBO_FRAME | \
+ DEV_RX_OFFLOAD_CRC_STRIP | \
+ DEV_RX_OFFLOAD_CHECKSUM)
+
+/** Port Tx offloads capabilities */
+#define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
+ DEV_TX_OFFLOAD_UDP_CKSUM | \
+ DEV_TX_OFFLOAD_TCP_CKSUM)
+
static const char * const valid_args[] = {
MRVL_IFACE_NAME_ARG,
MRVL_CFG_ARG,
int queue_id;
int port_id;
uint64_t bytes_sent;
+ struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
};
-/*
- * Every tx queue should have dedicated shadow tx queue.
- *
- * Ports assigned by DPDK might not start at zero or be continuous so
- * as a workaround define shadow queues for each possible port so that
- * we eventually fit somewhere.
- */
-struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
-
static int mrvl_lcore_first;
static int mrvl_lcore_last;
static int mrvl_dev_num;
+static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
+static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
+ struct pp2_hif *hif, unsigned int core_id,
+ struct mrvl_shadow_txq *sq, int qid, int force);
+
static inline int
mrvl_get_bpool_size(int pp2_id, int pool_id)
{
return n;
}
+static int
+mrvl_init_hif(int core_id)
+{
+ struct pp2_hif_params params;
+ char match[MRVL_MATCH_LEN];
+ int ret;
+
+ ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
+ if (ret < 0) {
+ RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
+ return ret;
+ }
+
+ snprintf(match, sizeof(match), "hif-%d", ret);
+ memset(¶ms, 0, sizeof(params));
+ params.match = match;
+ params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
+ ret = pp2_hif_init(¶ms, &hifs[core_id]);
+ if (ret) {
+ RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+static inline struct pp2_hif*
+mrvl_get_hif(struct mrvl_priv *priv, int core_id)
+{
+ int ret;
+
+ if (likely(hifs[core_id] != NULL))
+ return hifs[core_id];
+
+ rte_spinlock_lock(&priv->lock);
+
+ ret = mrvl_init_hif(core_id);
+ if (ret < 0) {
+ RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
+ goto out;
+ }
+
+ if (core_id < mrvl_lcore_first)
+ mrvl_lcore_first = core_id;
+
+ if (core_id > mrvl_lcore_last)
+ mrvl_lcore_last = core_id;
+out:
+ rte_spinlock_unlock(&priv->lock);
+
+ return hifs[core_id];
+}
+
/**
* Configure rss based on dpdk rss configuration.
*
return -EINVAL;
}
- if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
+ if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
RTE_LOG(INFO, PMD,
"L2 CRC stripping is always enabled in hw\n");
- dev->data->dev_conf.rxmode.hw_strip_crc = 1;
+ dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
}
- if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
+ if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
return -EINVAL;
}
return -EINVAL;
}
- if (dev->data->dev_conf.rxmode.enable_scatter) {
+ if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
return -EINVAL;
}
- if (dev->data->dev_conf.rxmode.enable_lro) {
+ if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
RTE_LOG(INFO, PMD, "LRO not supported\n");
return -EINVAL;
}
- if (dev->data->dev_conf.rxmode.jumbo_frame)
+ if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
ETHER_HDR_LEN - ETHER_CRC_LEN;
if (ret < 0)
return ret;
+ ret = mrvl_configure_txqs(priv, dev->data->port_id,
+ dev->data->nb_tx_queues);
+ if (ret < 0)
+ return ret;
+
priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
priv->ppio_params.maintain_stats = 1;
priv->nb_rx_queues = dev->data->nb_rx_queues;
return -EINVAL;
if (!priv->ppio)
- return -EPERM;
+ return 0;
ret = pp2_ppio_set_mru(priv->ppio, mru);
if (ret)
{
struct mrvl_priv *priv = dev->data->dev_private;
char match[MRVL_MATCH_LEN];
- int ret;
+ int ret = 0, def_init_size;
snprintf(match, sizeof(match), "ppio-%d:%d",
priv->pp_id, priv->ppio_id);
priv->ppio_params.match = match;
- /*
- * Calculate the maximum bpool size for refill feature to 1.5 of the
- * configured size. In case the bpool size will exceed this value,
- * superfluous buffers will be removed
- */
- priv->bpool_max_size = priv->bpool_init_size +
- (priv->bpool_init_size >> 1);
/*
* Calculate the minimum bpool size for refill feature as follows:
* 2 default burst sizes multiply by number of rx queues.
*/
priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
+ /* In case initial bpool size configured in queues setup is
+ * smaller than minimum size add more buffers
+ */
+ def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
+ if (priv->bpool_init_size < def_init_size) {
+ int buffs_to_add = def_init_size - priv->bpool_init_size;
+
+ priv->bpool_init_size += buffs_to_add;
+ ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
+ if (ret)
+ RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
+ }
+
+ /*
+ * Calculate the maximum bpool size for refill feature as follows:
+ * maximum number of descriptors in rx queue multiply by number
+ * of rx queues plus minimum bpool size.
+ * In case the bpool size will exceed this value, superfluous buffers
+ * will be removed
+ */
+ priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
+ priv->bpool_min_size;
+
ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
if (ret) {
RTE_LOG(ERR, PMD, "Failed to init ppio\n");
static void
mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
{
- int i;
+ int i, j;
+ struct mrvl_txq *txq;
RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
- for (i = 0; i < RTE_MAX_LCORE; i++) {
- struct mrvl_shadow_txq *sq =
- &shadow_txqs[dev->data->port_id][i];
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ txq = (struct mrvl_txq *)dev->data->tx_queues[i];
+
+ for (j = 0; j < RTE_MAX_LCORE; j++) {
+ struct mrvl_shadow_txq *sq;
- while (sq->tail != sq->head) {
- uint64_t addr = cookie_addr_high |
+ if (!hifs[j])
+ continue;
+
+ sq = &txq->shadow_txqs[j];
+ mrvl_free_sent_buffers(txq->priv->ppio,
+ hifs[j], j, sq, txq->queue_id, 1);
+ while (sq->tail != sq->head) {
+ uint64_t addr = cookie_addr_high |
sq->ent[sq->tail].buff.cookie;
- rte_pktmbuf_free((struct rte_mbuf *)addr);
- sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
+ rte_pktmbuf_free(
+ (struct rte_mbuf *)addr);
+ sq->tail = (sq->tail + 1) &
+ MRVL_PP2_TX_SHADOWQ_MASK;
+ }
+ memset(sq, 0, sizeof(*sq));
}
-
- memset(sq, 0, sizeof(*sq));
}
}
mrvl_flush_bpool(struct rte_eth_dev *dev)
{
struct mrvl_priv *priv = dev->data->dev_private;
+ struct pp2_hif *hif;
uint32_t num;
int ret;
+ unsigned int core_id = rte_lcore_id();
+
+ if (core_id == LCORE_ID_ANY)
+ core_id = 0;
+
+ hif = mrvl_get_hif(priv, core_id);
ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
if (ret) {
struct pp2_buff_inf inf;
uint64_t addr;
- ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
- &inf);
+ ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
if (ret)
break;
pp2_cls_qos_tbl_deinit(priv->qos_tbl);
priv->qos_tbl = NULL;
}
- pp2_ppio_deinit(priv->ppio);
+ if (priv->ppio)
+ pp2_ppio_deinit(priv->ppio);
priv->ppio = NULL;
+
+ /* policer must be released after ppio deinitialization */
+ if (priv->policer) {
+ pp2_cls_plcr_deinit(priv->policer);
+ priv->policer = NULL;
+ }
}
/**
return -1;
if (!priv->ppio)
- return -EPERM;
+ return 0;
/*
* Maximum number of uc addresses can be tuned via kernel module mvpp2x
info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
- info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
- DEV_RX_OFFLOAD_VLAN_FILTER |
- DEV_RX_OFFLOAD_IPV4_CKSUM |
- DEV_RX_OFFLOAD_UDP_CKSUM |
- DEV_RX_OFFLOAD_TCP_CKSUM;
+ info->rx_offload_capa = MRVL_RX_OFFLOADS;
+ info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
- info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
- DEV_TX_OFFLOAD_UDP_CKSUM |
- DEV_TX_OFFLOAD_TCP_CKSUM;
+ info->tx_offload_capa = MRVL_TX_OFFLOADS;
+ info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
info->flow_type_rss_offloads = ETH_RSS_IPV4 |
ETH_RSS_NONFRAG_IPV4_TCP |
/* By default packets are dropped if no descriptors are available */
info->default_rxconf.rx_drop_en = 1;
+ info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
}
struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
int i, ret;
- unsigned int core_id = rte_lcore_id();
- struct pp2_hif *hif = hifs[core_id];
- struct pp2_bpool *bpool = rxq->priv->bpool;
+ unsigned int core_id;
+ struct pp2_hif *hif;
+ struct pp2_bpool *bpool;
+
+ core_id = rte_lcore_id();
+ if (core_id == LCORE_ID_ANY)
+ core_id = 0;
+
+ hif = mrvl_get_hif(rxq->priv, core_id);
+ if (!hif)
+ return -1;
+
+ bpool = rxq->priv->bpool;
ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
if (ret)
return -1;
}
+/**
+ * Check whether requested rx queue offloads match port offloads.
+ *
+ * @param
+ * dev Pointer to the device.
+ * @param
+ * requested Bitmap of the requested offloads.
+ *
+ * @return
+ * 1 if requested offloads are okay, 0 otherwise.
+ */
+static int
+mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
+{
+ uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
+ uint64_t supported = MRVL_RX_OFFLOADS;
+ uint64_t unsupported = requested & ~supported;
+ uint64_t missing = mandatory & ~requested;
+
+ if (unsupported) {
+ RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
+ "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
+ requested, supported);
+ return 0;
+ }
+
+ if (missing) {
+ RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
+ "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
+ requested, missing);
+ return 0;
+ }
+
+ return 1;
+}
+
/**
* DPDK callback to configure the receive queue.
*
* @param socket
* NUMA socket on which memory must be allocated.
* @param conf
- * Thresholds parameters (unused_).
+ * Thresholds parameters.
* @param mp
* Memory pool for buffer allocations.
*
static int
mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
unsigned int socket,
- const struct rte_eth_rxconf *conf __rte_unused,
+ const struct rte_eth_rxconf *conf,
struct rte_mempool *mp)
{
struct mrvl_priv *priv = dev->data->dev_private;
max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
int ret, tc, inq;
+ if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads))
+ return -ENOTSUP;
+
if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
/*
* Unknown TC mapping, mapping will not have a correct queue.
rxq->priv = priv;
rxq->mp = mp;
- rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
+ rxq->cksum_enabled =
+ dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
rxq->queue_id = idx;
rxq->port_id = dev->data->port_id;
mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
struct mrvl_rxq *q = rxq;
struct pp2_ppio_tc_params *tc_params;
int i, num, tc, inq;
+ struct pp2_hif *hif;
+ unsigned int core_id = rte_lcore_id();
- if (!q)
+ if (core_id == LCORE_ID_ANY)
+ core_id = 0;
+
+ hif = mrvl_get_hif(q->priv, core_id);
+
+ if (!q || !hif)
return;
tc = q->priv->rxq_map[q->queue_id].tc;
struct pp2_buff_inf inf;
uint64_t addr;
- pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
+ pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
addr = cookie_addr_high | inf.cookie;
rte_pktmbuf_free((struct rte_mbuf *)addr);
}
rte_free(q);
}
+/**
+ * Check whether requested tx queue offloads match port offloads.
+ *
+ * @param
+ * dev Pointer to the device.
+ * @param
+ * requested Bitmap of the requested offloads.
+ *
+ * @return
+ * 1 if requested offloads are okay, 0 otherwise.
+ */
+static int
+mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
+{
+ uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
+ uint64_t supported = MRVL_TX_OFFLOADS;
+ uint64_t unsupported = requested & ~supported;
+ uint64_t missing = mandatory & ~requested;
+
+ if (unsupported) {
+ RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
+ "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
+ requested, supported);
+ return 0;
+ }
+
+ if (missing) {
+ RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
+ "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
+ requested, missing);
+ return 0;
+ }
+
+ return 1;
+}
+
/**
* DPDK callback to configure the transmit queue.
*
* @param socket
* NUMA socket on which memory must be allocated.
* @param conf
- * Thresholds parameters (unused).
+ * Thresholds parameters.
*
* @return
* 0 on success, negative error value otherwise.
static int
mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
unsigned int socket,
- const struct rte_eth_txconf *conf __rte_unused)
+ const struct rte_eth_txconf *conf)
{
struct mrvl_priv *priv = dev->data->dev_private;
struct mrvl_txq *txq;
+ if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads))
+ return -ENOTSUP;
+
if (dev->data->tx_queues[idx]) {
rte_free(dev->data->tx_queues[idx]);
dev->data->tx_queues[idx] = NULL;
dev->data->tx_queues[idx] = txq;
priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
- priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
return 0;
}
struct pp2_bpool *bpool;
int i, ret, rx_done = 0;
int num;
+ struct pp2_hif *hif;
unsigned int core_id = rte_lcore_id();
- if (unlikely(!q->priv->ppio))
+ hif = mrvl_get_hif(q->priv, core_id);
+
+ if (unlikely(!q->priv->ppio || !hif))
return 0;
bpool = q->priv->bpool;
.cookie = (pp2_cookie_t)(uint64_t)mbuf,
};
- pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
+ pp2_bpool_put_buff(hif, bpool, &binf);
mrvl_port_bpool_size
[bpool->pp2_id][bpool->id][core_id]++;
q->drop_mac++;
q->priv->bpool_init_size);
for (i = 0; i < pkt_to_remove; i++) {
- pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
+ ret = pp2_bpool_get_buff(hif, bpool, &buff);
+ if (ret)
+ break;
mbuf = (struct rte_mbuf *)
(cookie_addr_high | buff.cookie);
rte_pktmbuf_free(mbuf);
}
mrvl_port_bpool_size
- [bpool->pp2_id][bpool->id][core_id] -=
- pkt_to_remove;
+ [bpool->pp2_id][bpool->id][core_id] -= i;
}
rte_spinlock_unlock(&q->priv->lock);
}
*/
static inline void
mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
- struct mrvl_shadow_txq *sq, int qid, int force)
+ unsigned int core_id, struct mrvl_shadow_txq *sq,
+ int qid, int force)
{
struct buff_release_entry *entry;
uint16_t nb_done = 0, num = 0, skip_bufs = 0;
- int i, core_id = rte_lcore_id();
+ int i;
pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
sq->size -= num;
num = 0;
+ skip_bufs = 0;
}
if (likely(num)) {
mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
struct mrvl_txq *q = txq;
- struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
- struct pp2_hif *hif = hifs[rte_lcore_id()];
+ struct mrvl_shadow_txq *sq;
+ struct pp2_hif *hif;
struct pp2_ppio_desc descs[nb_pkts];
+ unsigned int core_id = rte_lcore_id();
int i, ret, bytes_sent = 0;
uint16_t num, sq_free_size;
uint64_t addr;
- if (unlikely(!q->priv->ppio))
+ hif = mrvl_get_hif(q->priv, core_id);
+ sq = &q->shadow_txqs[core_id];
+
+ if (unlikely(!q->priv->ppio || !hif))
return 0;
if (sq->size)
- mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
+ mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
+ sq, q->queue_id, 0);
sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
if (unlikely(nb_pkts > sq_free_size)) {
sq->ent[sq->head].buff.addr =
rte_mbuf_data_iova_default(mbuf);
sq->ent[sq->head].bpool =
- (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
- NULL : mrvl_port_to_bpool_lookup[mbuf->port];
+ (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
+ mbuf->refcnt > 1)) ? NULL :
+ mrvl_port_to_bpool_lookup[mbuf->port];
sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
sq->size++;
return 0;
}
-/**
- * Initialize per-lcore MUSDK hardware interfaces (hifs).
- *
- * @return
- * 0 on success, negative error value otherwise.
- */
-static int
-mrvl_init_hifs(void)
-{
- struct pp2_hif_params params;
- char match[MRVL_MATCH_LEN];
- int i, ret;
-
- RTE_LCORE_FOREACH(i) {
- ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
- if (ret < 0)
- return ret;
-
- snprintf(match, sizeof(match), "hif-%d", ret);
- memset(¶ms, 0, sizeof(params));
- params.match = match;
- params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
- ret = pp2_hif_init(¶ms, &hifs[i]);
- if (ret) {
- RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
- return ret;
- }
- }
-
- return 0;
-}
-
/**
* Deinitialize per-lcore MUSDK hardware interfaces (hifs).
*/
{
int i;
- RTE_LCORE_FOREACH(i) {
+ for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
if (hifs[i])
pp2_hif_deinit(hifs[i]);
}
memset(hifs, 0, sizeof(hifs));
}
-static void mrvl_set_first_last_cores(int core_id)
-{
- if (core_id < mrvl_lcore_first)
- mrvl_lcore_first = core_id;
-
- if (core_id > mrvl_lcore_last)
- mrvl_lcore_last = core_id;
-}
-
/**
* DPDK callback to register the virtual device.
*
struct rte_kvargs *kvlist;
struct mrvl_ifnames ifnames;
int ret = -EINVAL;
- uint32_t i, ifnum, cfgnum, core_id;
+ uint32_t i, ifnum, cfgnum;
const char *params;
params = rte_vdev_device_args(vdev);
goto out_deinit_dma;
}
- ret = mrvl_init_hifs();
- if (ret)
- goto out_deinit_hifs;
+ memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
+ memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
+
+ mrvl_lcore_first = RTE_MAX_LCORE;
+ mrvl_lcore_last = 0;
init_devices:
for (i = 0; i < ifnum; i++) {
rte_kvargs_free(kvlist);
- memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
-
- mrvl_lcore_first = RTE_MAX_LCORE;
- mrvl_lcore_last = 0;
-
- RTE_LCORE_FOREACH(core_id) {
- mrvl_set_first_last_cores(core_id);
- }
-
return 0;
out_cleanup:
for (; i > 0; i--)
mrvl_eth_dev_destroy(ifnames.names[i]);
-out_deinit_hifs:
- if (mrvl_dev_num == 0) {
- mrvl_deinit_hifs();
+
+ if (mrvl_dev_num == 0)
mrvl_deinit_pp2();
- }
out_deinit_dma:
if (mrvl_dev_num == 0)
mv_sys_dma_mem_destroy();
git.droids-corp.org / dpdk.git / blobdiff