#define MRVL_MUSDK_HIFS_RESERVED 0x0F
/* bitmask with reserved bpools */
#define MRVL_MUSDK_BPOOLS_RESERVED 0x07
+/* bitmask with reserved kernel RSS tables */
+#define MRVL_MUSDK_RSS_RESERVED 0x01
/* maximum number of available hifs */
#define MRVL_MUSDK_HIFS_MAX 9
-#define MRVL_MAC_ADDRS_MAX 1
+/* prefetch shift */
+#define MRVL_MUSDK_PREFETCH_SHIFT 2
+
+/* TCAM has 25 entries reserved for uc/mc filter entries */
+#define MRVL_MAC_ADDRS_MAX 25
#define MRVL_MATCH_LEN 16
#define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
/* Maximum allowable packet size */
MRVL_MUSDK_BPOOLS_RESERVED
};
+struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
+int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
+/*
+ * To use buffer harvesting based on loopback port shadow queue structure
+ * was introduced for buffers information bookkeeping.
+ *
+ * Before sending the packet, related buffer information (pp2_buff_inf) is
+ * stored in shadow queue. After packet is transmitted no longer used
+ * packet buffer is released back to it's original hardware pool,
+ * on condition it originated from interface.
+ * In case it was generated by application itself i.e: mbuf->port field is
+ * 0xff then its released to software mempool.
+ */
+struct mrvl_shadow_txq {
+ int head; /* write index - used when sending buffers */
+ int tail; /* read index - used when releasing buffers */
+ u16 size; /* queue occupied size */
+ u16 num_to_release; /* number of buffers sent, that can be released */
+ struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
+};
+
struct mrvl_rxq {
struct mrvl_priv *priv;
struct rte_mempool *mp;
int queue_id;
int port_id;
+ int cksum_enabled;
};
struct mrvl_txq {
int port_id;
};
+/*
+ * Every tx queue should have dedicated shadow tx queue.
+ *
+ * Ports assigned by DPDK might not start at zero or be continuous so
+ * as a workaround define shadow queues for each possible port so that
+ * we eventually fit somewhere.
+ */
+struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
+
/** Number of ports configured. */
int mrvl_ports_nb;
+static int mrvl_lcore_first;
+static int mrvl_lcore_last;
+
+static inline int
+mrvl_get_bpool_size(int pp2_id, int pool_id)
+{
+ int i;
+ int size = 0;
+
+ for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
+ size += mrvl_port_bpool_size[pp2_id][pool_id][i];
+
+ return size;
+}
static inline int
mrvl_reserve_bit(int *bitmap, int max)
return n;
}
+/**
+ * Configure rss based on dpdk rss configuration.
+ *
+ * @param priv
+ * Pointer to private structure.
+ * @param rss_conf
+ * Pointer to RSS configuration.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
+{
+ if (rss_conf->rss_key)
+ RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
+
+ if (rss_conf->rss_hf == 0) {
+ priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
+ } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
+ priv->ppio_params.inqs_params.hash_type =
+ PP2_PPIO_HASH_T_2_TUPLE;
+ } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
+ priv->ppio_params.inqs_params.hash_type =
+ PP2_PPIO_HASH_T_5_TUPLE;
+ priv->rss_hf_tcp = 1;
+ } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
+ priv->ppio_params.inqs_params.hash_type =
+ PP2_PPIO_HASH_T_5_TUPLE;
+ priv->rss_hf_tcp = 0;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/**
* Ethernet device configuration.
*
- * Prepare the driver for a given number of TX and RX queues.
+ * Prepare the driver for a given number of TX and RX queues and
+ * configure RSS.
*
* @param dev
* Pointer to Ethernet device structure.
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
- if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE) {
+ if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
+ dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
dev->data->dev_conf.rxmode.mq_mode);
return -EINVAL;
return -EINVAL;
}
+ if (dev->data->dev_conf.rxmode.jumbo_frame)
+ dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
+ ETHER_HDR_LEN - ETHER_CRC_LEN;
+
ret = mrvl_configure_rxqs(priv, dev->data->port_id,
dev->data->nb_rx_queues);
if (ret < 0)
priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
priv->nb_rx_queues = dev->data->nb_rx_queues;
- return 0;
+ if (dev->data->nb_rx_queues == 1 &&
+ dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
+ RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
+ priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
+
+ return 0;
+ }
+
+ return mrvl_configure_rss(priv,
+ &dev->data->dev_conf.rx_adv_conf.rss_conf);
+}
+
+/**
+ * DPDK callback to change the MTU.
+ *
+ * Setting the MTU affects hardware MRU (packets larger than the MRU
+ * will be dropped).
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param mtu
+ * New MTU.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ /* extra MV_MH_SIZE bytes are required for Marvell tag */
+ uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
+ int ret;
+
+ if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
+ return -EINVAL;
+
+ ret = pp2_ppio_set_mru(priv->ppio, mru);
+ if (ret)
+ return ret;
+
+ return pp2_ppio_set_mtu(priv->ppio, mtu);
}
/**
if (ret)
return ret;
+ /*
+ * mtu/mru can be updated if pp2_ppio_enable() was called at least once
+ * as pp2_ppio_enable() changes port->t_mode from default 0 to
+ * PP2_TRAFFIC_INGRESS_EGRESS.
+ *
+ * Set mtu to default DPDK value here.
+ */
+ ret = mrvl_mtu_set(dev, dev->data->mtu);
+ if (ret)
+ pp2_ppio_disable(priv->ppio);
+
dev->data->dev_link.link_status = ETH_LINK_UP;
return ret;
if (ret)
return ret;
+ /*
+ * In case there are some some stale uc/mc mac addresses flush them
+ * here. It cannot be done during mrvl_dev_close() as port information
+ * is already gone at that point (due to pp2_ppio_deinit() in
+ * mrvl_dev_stop()).
+ */
+ if (!priv->uc_mc_flushed) {
+ ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
+ if (ret) {
+ RTE_LOG(ERR, PMD,
+ "Failed to flush uc/mc filter list\n");
+ goto out;
+ }
+ priv->uc_mc_flushed = 1;
+ }
+
+ if (!priv->vlan_flushed) {
+ ret = pp2_ppio_flush_vlan(priv->ppio);
+ if (ret) {
+ RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
+ /*
+ * TODO
+ * once pp2_ppio_flush_vlan() is supported jump to out
+ * goto out;
+ */
+ }
+ priv->vlan_flushed = 1;
+ }
+
/* For default QoS config, don't start classifier. */
if (mrvl_qos_cfg) {
ret = mrvl_start_qos_mapping(priv);
}
}
+/**
+ * Flush transmit shadow queues.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ */
+static void
+mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
+{
+ int i;
+
+ RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
+ for (i = 0; i < RTE_MAX_LCORE; i++) {
+ struct mrvl_shadow_txq *sq =
+ &shadow_txqs[dev->data->port_id][i];
+
+ while (sq->tail != sq->head) {
+ uint64_t addr = cookie_addr_high |
+ sq->ent[sq->tail].buff.cookie;
+ rte_pktmbuf_free((struct rte_mbuf *)addr);
+ sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
+ }
+
+ memset(sq, 0, sizeof(*sq));
+ }
+}
+
/**
* Flush hardware bpool (buffer-pool).
*
mrvl_dev_set_link_down(dev);
mrvl_flush_rx_queues(dev);
+ mrvl_flush_tx_shadow_queues(dev);
if (priv->qos_tbl)
pp2_cls_qos_tbl_deinit(priv->qos_tbl);
pp2_ppio_deinit(priv->ppio);
mrvl_flush_bpool(dev);
}
+/**
+ * DPDK callback to retrieve physical link information.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param wait_to_complete
+ * Wait for request completion (ignored).
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
+{
+ /*
+ * TODO
+ * once MUSDK provides necessary API use it here
+ */
+ struct ethtool_cmd edata;
+ struct ifreq req;
+ int ret, fd;
+
+ edata.cmd = ETHTOOL_GSET;
+
+ strcpy(req.ifr_name, dev->data->name);
+ req.ifr_data = (void *)&edata;
+
+ fd = socket(AF_INET, SOCK_DGRAM, 0);
+ if (fd == -1)
+ return -EFAULT;
+
+ ret = ioctl(fd, SIOCETHTOOL, &req);
+ if (ret == -1) {
+ close(fd);
+ return -EFAULT;
+ }
+
+ close(fd);
+
+ switch (ethtool_cmd_speed(&edata)) {
+ case SPEED_10:
+ dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
+ break;
+ case SPEED_100:
+ dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
+ break;
+ case SPEED_1000:
+ dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
+ break;
+ case SPEED_10000:
+ dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
+ break;
+ default:
+ dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
+ }
+
+ dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
+ ETH_LINK_HALF_DUPLEX;
+ dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
+ ETH_LINK_FIXED;
+
+ return 0;
+}
+
+/**
+ * DPDK callback to enable promiscuous mode.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ */
+static void
+mrvl_promiscuous_enable(struct rte_eth_dev *dev)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ int ret;
+
+ ret = pp2_ppio_set_uc_promisc(priv->ppio, 1);
+ if (ret)
+ RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
+}
+
+/**
+ * DPDK callback to enable allmulti mode.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ */
+static void
+mrvl_allmulticast_enable(struct rte_eth_dev *dev)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ int ret;
+
+ ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
+ if (ret)
+ RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
+}
+
+/**
+ * DPDK callback to disable promiscuous mode.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ */
+static void
+mrvl_promiscuous_disable(struct rte_eth_dev *dev)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ int ret;
+
+ ret = pp2_ppio_set_uc_promisc(priv->ppio, 0);
+ if (ret)
+ RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
+}
+
+/**
+ * DPDK callback to disable allmulticast mode.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ */
+static void
+mrvl_allmulticast_disable(struct rte_eth_dev *dev)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ int ret;
+
+ ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
+ if (ret)
+ RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
+}
+
+/**
+ * DPDK callback to remove a MAC address.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param index
+ * MAC address index.
+ */
+static void
+mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ char buf[ETHER_ADDR_FMT_SIZE];
+ int ret;
+
+ ret = pp2_ppio_remove_mac_addr(priv->ppio,
+ dev->data->mac_addrs[index].addr_bytes);
+ if (ret) {
+ ether_format_addr(buf, sizeof(buf),
+ &dev->data->mac_addrs[index]);
+ RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
+ }
+}
+
+/**
+ * DPDK callback to add a MAC address.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param mac_addr
+ * MAC address to register.
+ * @param index
+ * MAC address index.
+ * @param vmdq
+ * VMDq pool index to associate address with (unused).
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
+ uint32_t index, uint32_t vmdq __rte_unused)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ char buf[ETHER_ADDR_FMT_SIZE];
+ int ret;
+
+ if (index == 0)
+ /* For setting index 0, mrvl_mac_addr_set() should be used.*/
+ return -1;
+
+ /*
+ * Maximum number of uc addresses can be tuned via kernel module mvpp2x
+ * parameter uc_filter_max. Maximum number of mc addresses is then
+ * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
+ * 21 respectively.
+ *
+ * If more than uc_filter_max uc addresses were added to filter list
+ * then NIC will switch to promiscuous mode automatically.
+ *
+ * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
+ * were added to filter list then NIC will switch to all-multicast mode
+ * automatically.
+ */
+ ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
+ if (ret) {
+ ether_format_addr(buf, sizeof(buf), mac_addr);
+ RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
+ return -1;
+ }
+
+ return 0;
+}
+
/**
* DPDK callback to set the primary MAC address.
*
mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
struct rte_eth_dev_info *info)
{
+ info->speed_capa = ETH_LINK_SPEED_10M |
+ ETH_LINK_SPEED_100M |
+ ETH_LINK_SPEED_1G |
+ ETH_LINK_SPEED_10G;
+
info->max_rx_queues = MRVL_PP2_RXQ_MAX;
info->max_tx_queues = MRVL_PP2_TXQ_MAX;
info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
+ info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_VLAN_FILTER |
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM;
+
+ info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_UDP_CKSUM |
+ DEV_TX_OFFLOAD_TCP_CKSUM;
+
+ info->flow_type_rss_offloads = ETH_RSS_IPV4 |
+ ETH_RSS_NONFRAG_IPV4_TCP |
+ ETH_RSS_NONFRAG_IPV4_UDP;
+
/* By default packets are dropped if no descriptors are available */
info->default_rxconf.rx_drop_en = 1;
info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
}
+/**
+ * Return supported packet types.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure (unused).
+ *
+ * @return
+ * Const pointer to the table with supported packet types.
+ */
+static const uint32_t *
+mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
+{
+ static const uint32_t ptypes[] = {
+ RTE_PTYPE_L2_ETHER,
+ RTE_PTYPE_L3_IPV4,
+ RTE_PTYPE_L3_IPV4_EXT,
+ RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
+ RTE_PTYPE_L3_IPV6,
+ RTE_PTYPE_L3_IPV6_EXT,
+ RTE_PTYPE_L2_ETHER_ARP,
+ RTE_PTYPE_L4_TCP,
+ RTE_PTYPE_L4_UDP
+ };
+
+ return ptypes;
+}
+
/**
* DPDK callback to get information about specific receive queue.
*
priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
}
+/**
+ * DPDK callback to Configure a VLAN filter.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param vlan_id
+ * VLAN ID to filter.
+ * @param on
+ * Toggle filter.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+
+ return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
+ pp2_ppio_remove_vlan(priv->ppio, vlan_id);
+}
+
/**
* Release buffers to hardware bpool (buffer-pool)
*
}
pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
+ mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
if (i != num)
goto out;
rxq->priv = priv;
rxq->mp = mp;
+ rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
rxq->queue_id = idx;
rxq->port_id = dev->data->port_id;
+ mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
tc = priv->rxq_map[rxq->queue_id].tc,
inq = priv->rxq_map[rxq->queue_id].inq;
rte_free(q);
}
+/**
+ * Update RSS hash configuration
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param rss_conf
+ * Pointer to RSS configuration.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_rss_hash_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+
+ return mrvl_configure_rss(priv, rss_conf);
+}
+
+/**
+ * DPDK callback to get RSS hash configuration.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @rss_conf
+ * Pointer to RSS configuration.
+ *
+ * @return
+ * Always 0.
+ */
+static int
+mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf)
+{
+ struct mrvl_priv *priv = dev->data->dev_private;
+ enum pp2_ppio_hash_type hash_type =
+ priv->ppio_params.inqs_params.hash_type;
+
+ rss_conf->rss_key = NULL;
+
+ if (hash_type == PP2_PPIO_HASH_T_NONE)
+ rss_conf->rss_hf = 0;
+ else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
+ rss_conf->rss_hf = ETH_RSS_IPV4;
+ else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
+ rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
+ else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
+ rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
+
+ return 0;
+}
+
static const struct eth_dev_ops mrvl_ops = {
.dev_configure = mrvl_dev_configure,
.dev_start = mrvl_dev_start,
.dev_set_link_up = mrvl_dev_set_link_up,
.dev_set_link_down = mrvl_dev_set_link_down,
.dev_close = mrvl_dev_close,
+ .link_update = mrvl_link_update,
+ .promiscuous_enable = mrvl_promiscuous_enable,
+ .allmulticast_enable = mrvl_allmulticast_enable,
+ .promiscuous_disable = mrvl_promiscuous_disable,
+ .allmulticast_disable = mrvl_allmulticast_disable,
+ .mac_addr_remove = mrvl_mac_addr_remove,
+ .mac_addr_add = mrvl_mac_addr_add,
.mac_addr_set = mrvl_mac_addr_set,
+ .mtu_set = mrvl_mtu_set,
.dev_infos_get = mrvl_dev_infos_get,
+ .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
.rxq_info_get = mrvl_rxq_info_get,
.txq_info_get = mrvl_txq_info_get,
+ .vlan_filter_set = mrvl_vlan_filter_set,
.rx_queue_setup = mrvl_rx_queue_setup,
.rx_queue_release = mrvl_rx_queue_release,
.tx_queue_setup = mrvl_tx_queue_setup,
.tx_queue_release = mrvl_tx_queue_release,
+ .rss_hash_update = mrvl_rss_hash_update,
+ .rss_hash_conf_get = mrvl_rss_hash_conf_get,
};
+/**
+ * Return packet type information and l3/l4 offsets.
+ *
+ * @param desc
+ * Pointer to the received packet descriptor.
+ * @param l3_offset
+ * l3 packet offset.
+ * @param l4_offset
+ * l4 packet offset.
+ *
+ * @return
+ * Packet type information.
+ */
+static inline uint64_t
+mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
+ uint8_t *l3_offset, uint8_t *l4_offset)
+{
+ enum pp2_inq_l3_type l3_type;
+ enum pp2_inq_l4_type l4_type;
+ uint64_t packet_type;
+
+ pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
+ pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
+
+ packet_type = RTE_PTYPE_L2_ETHER;
+
+ switch (l3_type) {
+ case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
+ packet_type |= RTE_PTYPE_L3_IPV4;
+ break;
+ case PP2_INQ_L3_TYPE_IPV4_OK:
+ packet_type |= RTE_PTYPE_L3_IPV4_EXT;
+ break;
+ case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
+ packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ break;
+ case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
+ packet_type |= RTE_PTYPE_L3_IPV6;
+ break;
+ case PP2_INQ_L3_TYPE_IPV6_EXT:
+ packet_type |= RTE_PTYPE_L3_IPV6_EXT;
+ break;
+ case PP2_INQ_L3_TYPE_ARP:
+ packet_type |= RTE_PTYPE_L2_ETHER_ARP;
+ /*
+ * In case of ARP l4_offset is set to wrong value.
+ * Set it to proper one so that later on mbuf->l3_len can be
+ * calculated subtracting l4_offset and l3_offset.
+ */
+ *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
+ break;
+ default:
+ RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
+ break;
+ }
+
+ switch (l4_type) {
+ case PP2_INQ_L4_TYPE_TCP:
+ packet_type |= RTE_PTYPE_L4_TCP;
+ break;
+ case PP2_INQ_L4_TYPE_UDP:
+ packet_type |= RTE_PTYPE_L4_UDP;
+ break;
+ default:
+ RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
+ break;
+ }
+
+ return packet_type;
+}
+
+/**
+ * Get offload information from the received packet descriptor.
+ *
+ * @param desc
+ * Pointer to the received packet descriptor.
+ *
+ * @return
+ * Mbuf offload flags.
+ */
+static inline uint64_t
+mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
+{
+ uint64_t flags;
+ enum pp2_inq_desc_status status;
+
+ status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
+ if (unlikely(status != PP2_DESC_ERR_OK))
+ flags = PKT_RX_IP_CKSUM_BAD;
+ else
+ flags = PKT_RX_IP_CKSUM_GOOD;
+
+ status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
+ if (unlikely(status != PP2_DESC_ERR_OK))
+ flags |= PKT_RX_L4_CKSUM_BAD;
+ else
+ flags |= PKT_RX_L4_CKSUM_GOOD;
+
+ return flags;
+}
+
+/**
+ * DPDK callback for receive.
+ *
+ * @param rxq
+ * Generic pointer to the receive queue.
+ * @param rx_pkts
+ * Array to store received packets.
+ * @param nb_pkts
+ * Maximum number of packets in array.
+ *
+ * @return
+ * Number of packets successfully received.
+ */
+static uint16_t
+mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+ struct mrvl_rxq *q = rxq;
+ struct pp2_ppio_desc descs[nb_pkts];
+ struct pp2_bpool *bpool;
+ int i, ret, rx_done = 0;
+ int num;
+ unsigned int core_id = rte_lcore_id();
+
+ if (unlikely(!q->priv->ppio))
+ return 0;
+
+ bpool = q->priv->bpool;
+
+ ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
+ q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
+ if (unlikely(ret < 0)) {
+ RTE_LOG(ERR, PMD, "Failed to receive packets\n");
+ return 0;
+ }
+ mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
+
+ for (i = 0; i < nb_pkts; i++) {
+ struct rte_mbuf *mbuf;
+ uint8_t l3_offset, l4_offset;
+ enum pp2_inq_desc_status status;
+ uint64_t addr;
+
+ if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
+ struct pp2_ppio_desc *pref_desc;
+ u64 pref_addr;
+
+ pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
+ pref_addr = cookie_addr_high |
+ pp2_ppio_inq_desc_get_cookie(pref_desc);
+ rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
+ rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
+ }
+
+ addr = cookie_addr_high |
+ pp2_ppio_inq_desc_get_cookie(&descs[i]);
+ mbuf = (struct rte_mbuf *)addr;
+ rte_pktmbuf_reset(mbuf);
+
+ /* drop packet in case of mac, overrun or resource error */
+ status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
+ if (unlikely(status != PP2_DESC_ERR_OK)) {
+ struct pp2_buff_inf binf = {
+ .addr = rte_mbuf_data_dma_addr_default(mbuf),
+ .cookie = (pp2_cookie_t)(uint64_t)mbuf,
+ };
+
+ pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
+ mrvl_port_bpool_size
+ [bpool->pp2_id][bpool->id][core_id]++;
+ continue;
+ }
+
+ mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
+ mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
+ mbuf->data_len = mbuf->pkt_len;
+ mbuf->port = q->port_id;
+ mbuf->packet_type =
+ mrvl_desc_to_packet_type_and_offset(&descs[i],
+ &l3_offset,
+ &l4_offset);
+ mbuf->l2_len = l3_offset;
+ mbuf->l3_len = l4_offset - l3_offset;
+
+ if (likely(q->cksum_enabled))
+ mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
+
+ rx_pkts[rx_done++] = mbuf;
+ }
+
+ if (rte_spinlock_trylock(&q->priv->lock) == 1) {
+ num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
+
+ if (unlikely(num <= q->priv->bpool_min_size ||
+ (!rx_done && num < q->priv->bpool_init_size))) {
+ ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
+ if (ret)
+ RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
+ } else if (unlikely(num > q->priv->bpool_max_size)) {
+ int i;
+ int pkt_to_remove = num - q->priv->bpool_init_size;
+ struct rte_mbuf *mbuf;
+ struct pp2_buff_inf buff;
+
+ RTE_LOG(DEBUG, PMD,
+ "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
+ bpool->pp2_id, q->priv->ppio->port_id,
+ bpool->id, pkt_to_remove, num,
+ q->priv->bpool_init_size);
+
+ for (i = 0; i < pkt_to_remove; i++) {
+ pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
+ mbuf = (struct rte_mbuf *)
+ (cookie_addr_high | buff.cookie);
+ rte_pktmbuf_free(mbuf);
+ }
+ mrvl_port_bpool_size
+ [bpool->pp2_id][bpool->id][core_id] -=
+ pkt_to_remove;
+ }
+ rte_spinlock_unlock(&q->priv->lock);
+ }
+
+ return rx_done;
+}
+
+/**
+ * Prepare offload information.
+ *
+ * @param ol_flags
+ * Offload flags.
+ * @param packet_type
+ * Packet type bitfield.
+ * @param l3_type
+ * Pointer to the pp2_ouq_l3_type structure.
+ * @param l4_type
+ * Pointer to the pp2_outq_l4_type structure.
+ * @param gen_l3_cksum
+ * Will be set to 1 in case l3 checksum is computed.
+ * @param l4_cksum
+ * Will be set to 1 in case l4 checksum is computed.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static inline int
+mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
+ enum pp2_outq_l3_type *l3_type,
+ enum pp2_outq_l4_type *l4_type,
+ int *gen_l3_cksum,
+ int *gen_l4_cksum)
+{
+ /*
+ * Based on ol_flags prepare information
+ * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
+ * for offloading.
+ */
+ if (ol_flags & PKT_TX_IPV4) {
+ *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
+ *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
+ } else if (ol_flags & PKT_TX_IPV6) {
+ *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
+ /* no checksum for ipv6 header */
+ *gen_l3_cksum = 0;
+ } else {
+ /* if something different then stop processing */
+ return -1;
+ }
+
+ ol_flags &= PKT_TX_L4_MASK;
+ if ((packet_type & RTE_PTYPE_L4_TCP) &&
+ ol_flags == PKT_TX_TCP_CKSUM) {
+ *l4_type = PP2_OUTQ_L4_TYPE_TCP;
+ *gen_l4_cksum = 1;
+ } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
+ ol_flags == PKT_TX_UDP_CKSUM) {
+ *l4_type = PP2_OUTQ_L4_TYPE_UDP;
+ *gen_l4_cksum = 1;
+ } else {
+ *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
+ /* no checksum for other type */
+ *gen_l4_cksum = 0;
+ }
+
+ return 0;
+}
+
+/**
+ * Release already sent buffers to bpool (buffer-pool).
+ *
+ * @param ppio
+ * Pointer to the port structure.
+ * @param hif
+ * Pointer to the MUSDK hardware interface.
+ * @param sq
+ * Pointer to the shadow queue.
+ * @param qid
+ * Queue id number.
+ * @param force
+ * Force releasing packets.
+ */
+static inline void
+mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
+ struct mrvl_shadow_txq *sq, int qid, int force)
+{
+ struct buff_release_entry *entry;
+ uint16_t nb_done = 0, num = 0, skip_bufs = 0;
+ int i, core_id = rte_lcore_id();
+
+ pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
+
+ sq->num_to_release += nb_done;
+
+ if (likely(!force &&
+ sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
+ return;
+
+ nb_done = sq->num_to_release;
+ sq->num_to_release = 0;
+
+ for (i = 0; i < nb_done; i++) {
+ entry = &sq->ent[sq->tail + num];
+ if (unlikely(!entry->buff.addr)) {
+ RTE_LOG(ERR, PMD,
+ "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
+ sq->tail, (u64)entry->buff.cookie,
+ (u64)entry->buff.addr);
+ skip_bufs = 1;
+ goto skip;
+ }
+
+ if (unlikely(!entry->bpool)) {
+ struct rte_mbuf *mbuf;
+
+ mbuf = (struct rte_mbuf *)
+ (cookie_addr_high | entry->buff.cookie);
+ rte_pktmbuf_free(mbuf);
+ skip_bufs = 1;
+ goto skip;
+ }
+
+ mrvl_port_bpool_size
+ [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
+ num++;
+ if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
+ goto skip;
+ continue;
+skip:
+ if (likely(num))
+ pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
+ num += skip_bufs;
+ sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
+ sq->size -= num;
+ num = 0;
+ }
+
+ if (likely(num)) {
+ pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
+ sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
+ sq->size -= num;
+ }
+}
+
+/**
+ * DPDK callback for transmit.
+ *
+ * @param txq
+ * Generic pointer transmit queue.
+ * @param tx_pkts
+ * Packets to transmit.
+ * @param nb_pkts
+ * Number of packets in array.
+ *
+ * @return
+ * Number of packets successfully transmitted.
+ */
+static uint16_t
+mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
+{
+ struct mrvl_txq *q = txq;
+ struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
+ struct pp2_hif *hif = hifs[rte_lcore_id()];
+ struct pp2_ppio_desc descs[nb_pkts];
+ int i, ret;
+ uint16_t num, sq_free_size;
+
+ if (unlikely(!q->priv->ppio))
+ return 0;
+
+ if (sq->size)
+ mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
+
+ sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
+ if (unlikely(nb_pkts > sq_free_size)) {
+ RTE_LOG(DEBUG, PMD,
+ "No room in shadow queue for %d packets! %d packets will be sent.\n",
+ nb_pkts, sq_free_size);
+ nb_pkts = sq_free_size;
+ }
+
+ for (i = 0; i < nb_pkts; i++) {
+ struct rte_mbuf *mbuf = tx_pkts[i];
+ int gen_l3_cksum, gen_l4_cksum;
+ enum pp2_outq_l3_type l3_type;
+ enum pp2_outq_l4_type l4_type;
+
+ if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
+ struct rte_mbuf *pref_pkt_hdr;
+
+ pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
+ rte_mbuf_prefetch_part1(pref_pkt_hdr);
+ rte_mbuf_prefetch_part2(pref_pkt_hdr);
+ }
+
+ sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
+ sq->ent[sq->head].buff.addr =
+ rte_mbuf_data_dma_addr_default(mbuf);
+ sq->ent[sq->head].bpool =
+ (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
+ NULL : mrvl_port_to_bpool_lookup[mbuf->port];
+ sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
+ sq->size++;
+
+ pp2_ppio_outq_desc_reset(&descs[i]);
+ pp2_ppio_outq_desc_set_phys_addr(&descs[i],
+ rte_pktmbuf_mtophys(mbuf));
+ pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
+ pp2_ppio_outq_desc_set_pkt_len(&descs[i],
+ rte_pktmbuf_pkt_len(mbuf));
+
+ /*
+ * in case unsupported ol_flags were passed
+ * do not update descriptor offload information
+ */
+ ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
+ &l3_type, &l4_type, &gen_l3_cksum,
+ &gen_l4_cksum);
+ if (unlikely(ret))
+ continue;
+
+ pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
+ mbuf->l2_len,
+ mbuf->l2_len + mbuf->l3_len,
+ gen_l3_cksum, gen_l4_cksum);
+ }
+
+ num = nb_pkts;
+ pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
+ /* number of packets that were not sent */
+ if (unlikely(num > nb_pkts)) {
+ for (i = nb_pkts; i < num; i++) {
+ sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
+ MRVL_PP2_TX_SHADOWQ_MASK;
+ }
+ sq->size -= num - nb_pkts;
+ }
+
+ return nb_pkts;
+}
+
/**
* Initialize packet processor.
*
memset(&init_params, 0, sizeof(init_params));
init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
+ init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
return pp2_init(&init_params);
}
goto out_clear_bpool_bit;
priv->ppio_params.type = PP2_PPIO_T_NIC;
+ rte_spinlock_init(&priv->lock);
return priv;
out_clear_bpool_bit:
memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
req.ifr_addr.sa_data, ETHER_ADDR_LEN);
+ eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
+ eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
eth_dev->data->dev_private = priv;
eth_dev->device = &vdev->device;
eth_dev->dev_ops = &mrvl_ops;
}
}
+static void mrvl_set_first_last_cores(int core_id)
+{
+ if (core_id < mrvl_lcore_first)
+ mrvl_lcore_first = core_id;
+
+ if (core_id > mrvl_lcore_last)
+ mrvl_lcore_last = core_id;
+}
+
/**
* DPDK callback to register the virtual device.
*
struct rte_kvargs *kvlist;
const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
int ret = -EINVAL;
- uint32_t i, ifnum, cfgnum;
+ uint32_t i, ifnum, cfgnum, core_id;
const char *params;
params = rte_vdev_device_args(vdev);
rte_kvargs_free(kvlist);
+ memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
+
+ mrvl_lcore_first = RTE_MAX_LCORE;
+ mrvl_lcore_last = 0;
+
+ RTE_LCORE_FOREACH(core_id) {
+ mrvl_set_first_last_cores(core_id);
+ }
+
return 0;
out_cleanup:
for (; i > 0; i--)
git.droids-corp.org / dpdk.git / blobdiff