/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017 Marvell International Ltd.
- * Copyright(c) 2017 Semihalf.
+ * Copyright(c) 2017-2021 Marvell International Ltd.
+ * Copyright(c) 2017-2021 Semihalf.
* All rights reserved.
*/
#include <rte_string_fns.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include <rte_kvargs.h>
#include <rte_log.h>
#include <rte_malloc.h>
/* bitmask with reserved bpools */
#define MRVL_MUSDK_BPOOLS_RESERVED 0x07
/* bitmask with reserved kernel RSS tables */
-#define MRVL_MUSDK_RSS_RESERVED 0x01
+#define MRVL_MUSDK_RSS_RESERVED 0x0F
/* maximum number of available hifs */
#define MRVL_MUSDK_HIFS_MAX 9
/* prefetch shift */
#define MRVL_MUSDK_PREFETCH_SHIFT 2
-/* TCAM has 25 entries reserved for uc/mc filter entries */
-#define MRVL_MAC_ADDRS_MAX 25
+/* TCAM has 25 entries reserved for uc/mc filter entries
+ * + 1 for primary mac address
+ */
+#define MRVL_MAC_ADDRS_MAX (1 + 25)
#define MRVL_MATCH_LEN 16
#define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
/* Maximum allowable packet size */
DEV_RX_OFFLOAD_CHECKSUM)
/** Port Tx offloads capabilities */
-#define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
- DEV_TX_OFFLOAD_UDP_CKSUM | \
- DEV_TX_OFFLOAD_TCP_CKSUM | \
+#define MRVL_TX_OFFLOAD_CHECKSUM (DEV_TX_OFFLOAD_IPV4_CKSUM | \
+ DEV_TX_OFFLOAD_UDP_CKSUM | \
+ DEV_TX_OFFLOAD_TCP_CKSUM)
+#define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \
DEV_TX_OFFLOAD_MULTI_SEGS)
+#define MRVL_TX_PKT_OFFLOADS (PKT_TX_IP_CKSUM | \
+ PKT_TX_TCP_CKSUM | \
+ PKT_TX_UDP_CKSUM)
+
static const char * const valid_args[] = {
MRVL_IFACE_NAME_ARG,
MRVL_CFG_ARG,
static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
+static int dummy_pool_id[PP2_NUM_PKT_PROC];
+struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0};
struct mrvl_ifnames {
const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
static void mrvl_deinit_pp2(void);
static void mrvl_deinit_hifs(void);
+static int
+mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
+ uint32_t index, uint32_t vmdq __rte_unused);
+static int
+mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
+static int
+mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
+static int mrvl_promiscuous_enable(struct rte_eth_dev *dev);
+static int mrvl_allmulticast_enable(struct rte_eth_dev *dev);
#define MRVL_XSTATS_TBL_ENTRY(name) { \
#name, offsetof(struct pp2_ppio_statistics, name), \
MRVL_XSTATS_TBL_ENTRY(tx_errors)
};
+static inline int
+mrvl_reserve_bit(int *bitmap, int max)
+{
+ int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
+
+ if (n >= max)
+ return -1;
+
+ *bitmap |= 1 << n;
+
+ return n;
+}
+
+static int
+mrvl_pp2_fixup_init(void)
+{
+ struct pp2_bpool_params bpool_params;
+ char name[15];
+ int err, i;
+
+ memset(dummy_pool, 0, sizeof(dummy_pool));
+ for (i = 0; i < pp2_get_num_inst(); i++) {
+ dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i],
+ PP2_BPOOL_NUM_POOLS);
+ if (dummy_pool_id[i] < 0) {
+ MRVL_LOG(ERR, "Can't find free pool\n");
+ return -1;
+ }
+
+ memset(name, 0, sizeof(name));
+ snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]);
+ memset(&bpool_params, 0, sizeof(bpool_params));
+ bpool_params.match = name;
+ bpool_params.buff_len = MRVL_PKT_OFFS;
+ bpool_params.dummy_short_pool = 1;
+ err = pp2_bpool_init(&bpool_params, &dummy_pool[i]);
+ if (err != 0 || !dummy_pool[i]) {
+ MRVL_LOG(ERR, "BPool init failed!\n");
+ used_bpools[i] &= ~(1 << dummy_pool_id[i]);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * Initialize packet processor.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int
+mrvl_init_pp2(void)
+{
+ struct pp2_init_params init_params;
+ int err;
+
+ memset(&init_params, 0, sizeof(init_params));
+ init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
+ init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
+ init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
+ if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs)
+ memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs,
+ sizeof(struct pp2_parse_udfs));
+ err = pp2_init(&init_params);
+ if (err != 0) {
+ MRVL_LOG(ERR, "PP2 init failed");
+ return -1;
+ }
+
+ err = mrvl_pp2_fixup_init();
+ if (err != 0) {
+ MRVL_LOG(ERR, "PP2 fixup init failed");
+ return -1;
+ }
+
+ return 0;
+}
+
+static void
+mrvl_pp2_fixup_deinit(void)
+{
+ int i;
+
+ for (i = 0; i < PP2_NUM_PKT_PROC; i++) {
+ if (!dummy_pool[i])
+ continue;
+ pp2_bpool_deinit(dummy_pool[i]);
+ used_bpools[i] &= ~(1 << dummy_pool_id[i]);
+ }
+}
+
+/**
+ * Deinitialize packet processor.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static void
+mrvl_deinit_pp2(void)
+{
+ mrvl_pp2_fixup_deinit();
+ pp2_deinit();
+}
+
static inline void
mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf)
{
sq->size++;
}
+/**
+ * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
+ */
+static void
+mrvl_deinit_hifs(void)
+{
+ int i;
+
+ for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
+ if (hifs[i])
+ pp2_hif_deinit(hifs[i]);
+ }
+ used_hifs = MRVL_MUSDK_HIFS_RESERVED;
+ memset(hifs, 0, sizeof(hifs));
+}
+
static inline void
mrvl_fill_desc(struct pp2_ppio_desc *desc, struct rte_mbuf *buf)
{
return size;
}
-static inline int
-mrvl_reserve_bit(int *bitmap, int max)
-{
- int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
-
- if (n >= max)
- return -1;
-
- *bitmap |= 1 << n;
-
- return n;
-}
-
static int
mrvl_init_hif(int core_id)
{
}
return mrvl_configure_rss(priv,
- &dev->data->dev_conf.rx_adv_conf.rss_conf);
+ &dev->data->dev_conf.rx_adv_conf.rss_conf);
}
/**
* when this feature has not been enabled/supported so far
* (TODO check scattered_rx flag here once scattered RX is supported).
*/
- if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
- mru = mbuf_data_size - MRVL_PKT_OFFS;
+ if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) {
+ mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS;
mtu = MRVL_PP2_MRU_TO_MTU(mru);
MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
"by current mbuf size: %u. Set MTU to %u, MRU to %u",
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
- if (!priv->ppio)
- return -EPERM;
+ if (!priv->ppio) {
+ dev->data->dev_link.link_status = ETH_LINK_UP;
+ return 0;
+ }
ret = pp2_ppio_enable(priv->ppio);
if (ret)
* Set mtu to default DPDK value here.
*/
ret = mrvl_mtu_set(dev, dev->data->mtu);
- if (ret)
+ if (ret) {
pp2_ppio_disable(priv->ppio);
+ return ret;
+ }
- return ret;
+ dev->data->dev_link.link_status = ETH_LINK_UP;
+ return 0;
}
/**
mrvl_dev_set_link_down(struct rte_eth_dev *dev)
{
struct mrvl_priv *priv = dev->data->dev_private;
+ int ret;
- if (!priv->ppio)
- return -EPERM;
+ if (!priv->ppio) {
+ dev->data->dev_link.link_status = ETH_LINK_DOWN;
+ return 0;
+ }
+ ret = pp2_ppio_disable(priv->ppio);
+ if (ret)
+ return ret;
- return pp2_ppio_disable(priv->ppio);
+ dev->data->dev_link.link_status = ETH_LINK_DOWN;
+ return 0;
}
/**
return 0;
}
+/**
+ * Populate VLAN Filter configuration.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param on
+ * Toggle filter.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on)
+{
+ uint32_t j;
+ int ret;
+ struct rte_vlan_filter_conf *vfc;
+
+ vfc = &dev->data->vlan_filter_conf;
+ for (j = 0; j < RTE_DIM(vfc->ids); j++) {
+ uint64_t vlan;
+ uint64_t vbit;
+ uint64_t ids = vfc->ids[j];
+
+ if (ids == 0)
+ continue;
+
+ while (ids) {
+ vlan = 64 * j;
+ /* count trailing zeroes */
+ vbit = ~ids & (ids - 1);
+ /* clear least significant bit set */
+ ids ^= (ids ^ (ids - 1)) ^ vbit;
+ for (; vbit; vlan++)
+ vbit >>= 1;
+ ret = mrvl_vlan_filter_set(dev, vlan, on);
+ if (ret) {
+ MRVL_LOG(ERR, "Failed to setup VLAN filter\n");
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
/**
* DPDK callback to start the device.
*
struct mrvl_priv *priv = dev->data->dev_private;
char match[MRVL_MATCH_LEN];
int ret = 0, i, def_init_size;
+ struct rte_ether_addr *mac_addr;
if (priv->ppio)
return mrvl_dev_set_link_up(dev);
snprintf(match, sizeof(match), "ppio-%d:%d",
priv->pp_id, priv->ppio_id);
priv->ppio_params.match = match;
+ priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH;
+ if (mrvl_cfg)
+ priv->ppio_params.eth_start_hdr =
+ mrvl_cfg->port[dev->data->port_id].eth_start_hdr;
/*
* Calculate the minimum bpool size for refill feature as follows:
priv->uc_mc_flushed = 1;
}
- if (!priv->vlan_flushed) {
- ret = pp2_ppio_flush_vlan(priv->ppio);
- if (ret) {
- MRVL_LOG(ERR, "Failed to flush vlan list");
- /*
- * TODO
- * once pp2_ppio_flush_vlan() is supported jump to out
- * goto out;
- */
- }
- priv->vlan_flushed = 1;
- }
ret = mrvl_mtu_set(dev, dev->data->mtu);
if (ret)
MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
+ if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0]))
+ mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]);
+
+ for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) {
+ mac_addr = &dev->data->mac_addrs[i];
+
+ /* skip zero address */
+ if (rte_is_zero_ether_addr(mac_addr))
+ continue;
+
+ mrvl_mac_addr_add(dev, mac_addr, i, 0);
+ }
+
+ if (dev->data->all_multicast == 1)
+ mrvl_allmulticast_enable(dev);
+
+ if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
+ ret = mrvl_populate_vlan_table(dev, 1);
+ if (ret) {
+ MRVL_LOG(ERR, "Failed to populate VLAN table");
+ goto out;
+ }
+ }
+
/* For default QoS config, don't start classifier. */
- if (mrvl_qos_cfg &&
- mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
+ if (mrvl_cfg &&
+ mrvl_cfg->port[dev->data->port_id].use_global_defaults == 0) {
ret = mrvl_start_qos_mapping(priv);
if (ret) {
MRVL_LOG(ERR, "Failed to setup QoS mapping");
}
}
- ret = mrvl_dev_set_link_up(dev);
+ ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode);
if (ret) {
- MRVL_LOG(ERR, "Failed to set link up");
+ MRVL_LOG(ERR, "Failed to set loopback");
goto out;
}
+ if (dev->data->promiscuous == 1)
+ mrvl_promiscuous_enable(dev);
+
+ if (dev->data->dev_link.link_status == ETH_LINK_UP) {
+ ret = mrvl_dev_set_link_up(dev);
+ if (ret) {
+ MRVL_LOG(ERR, "Failed to set link up");
+ dev->data->dev_link.link_status = ETH_LINK_DOWN;
+ goto out;
+ }
+ }
+
/* start tx queues */
for (i = 0; i < dev->data->nb_tx_queues; i++) {
struct mrvl_txq *txq = dev->data->tx_queues[i];
unsigned int core_id = rte_lcore_id();
if (core_id == LCORE_ID_ANY)
- core_id = rte_get_master_lcore();
+ core_id = rte_get_main_lcore();
hif = mrvl_get_hif(priv, core_id);
* @param dev
* Pointer to Ethernet device structure.
*/
-static void
+static int
mrvl_dev_stop(struct rte_eth_dev *dev)
{
- mrvl_dev_set_link_down(dev);
+ return mrvl_dev_set_link_down(dev);
}
/**
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
- if (!priv->ppio)
- return 0;
-
if (priv->isolated)
+ return -ENOTSUP;
+
+ if (!priv->ppio)
return 0;
ret = pp2_ppio_set_promisc(priv->ppio, 1);
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
- if (!priv->ppio)
- return 0;
-
if (priv->isolated)
+ return -ENOTSUP;
+
+ if (!priv->ppio)
return 0;
ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
+ if (priv->isolated)
+ return -ENOTSUP;
+
if (!priv->ppio)
return 0;
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
+ if (priv->isolated)
+ return -ENOTSUP;
+
if (!priv->ppio)
return 0;
char buf[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
- if (!priv->ppio)
+ if (priv->isolated)
return;
- if (priv->isolated)
+ if (!priv->ppio)
return;
ret = pp2_ppio_remove_mac_addr(priv->ppio,
if (priv->isolated)
return -ENOTSUP;
+ if (!priv->ppio)
+ return 0;
+
if (index == 0)
/* For setting index 0, mrvl_mac_addr_set() should be used.*/
return -1;
- if (!priv->ppio)
- return 0;
-
/*
* Maximum number of uc addresses can be tuned via kernel module mvpp2x
* parameter uc_filter_max. Maximum number of mc addresses is then
struct mrvl_priv *priv = dev->data->dev_private;
int ret;
- if (!priv->ppio)
- return 0;
-
if (priv->isolated)
return -ENOTSUP;
+ if (!priv->ppio)
+ return 0;
+
ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
if (ret) {
char buf[RTE_ETHER_ADDR_FMT_SIZE];
{
struct mrvl_priv *priv = dev->data->dev_private;
- if (!priv->ppio)
- return -EPERM;
-
if (priv->isolated)
return -ENOTSUP;
+ if (!priv->ppio)
+ return 0;
+
return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
pp2_ppio_remove_vlan(priv->ppio, vlan_id);
}
+/**
+ * DPDK callback to Configure VLAN offload.
+ *
+ * @param dev
+ * Pointer to Ethernet device structure.
+ * @param mask
+ * VLAN offload mask.
+ *
+ * @return
+ * 0 on success, negative error value otherwise.
+ */
+static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask)
+{
+ uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
+ int ret;
+
+ if (mask & ETH_VLAN_STRIP_MASK)
+ MRVL_LOG(ERR, "VLAN stripping is not supported\n");
+
+ if (mask & ETH_VLAN_FILTER_MASK) {
+ if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
+ ret = mrvl_populate_vlan_table(dev, 1);
+ else
+ ret = mrvl_populate_vlan_table(dev, 0);
+
+ if (ret)
+ return ret;
+ }
+
+ if (mask & ETH_VLAN_EXTEND_MASK)
+ MRVL_LOG(ERR, "Extend VLAN not supported\n");
+
+ return 0;
+}
+
/**
* Release buffers to hardware bpool (buffer-pool)
*
static int
mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
{
- struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
- struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
+ struct buff_release_entry entries[num];
+ struct rte_mbuf *mbufs[num];
int i, ret;
unsigned int core_id;
struct pp2_hif *hif;
core_id = rte_lcore_id();
if (core_id == LCORE_ID_ANY)
- core_id = rte_get_master_lcore();
+ core_id = rte_get_main_lcore();
hif = mrvl_get_hif(rxq->priv, core_id);
if (!hif)
if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
!= cookie_addr_high) {
MRVL_LOG(ERR,
- "mbuf virtual addr high 0x%lx out of range",
- (uint64_t)mbufs[i] >> 32);
+ "mbuf virtual addr high is out of range "
+ "0x%x instead of 0x%x\n",
+ (uint32_t)((uint64_t)mbufs[i] >> 32),
+ (uint32_t)(cookie_addr_high >> 32));
goto out;
}
entries[i].buff.addr =
rte_mbuf_data_iova_default(mbufs[i]);
- entries[i].buff.cookie = (uint64_t)mbufs[i];
+ entries[i].buff.cookie = (uintptr_t)mbufs[i];
entries[i].bpool = bpool;
}
return -EFAULT;
}
- frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
+ frame_size = buf_size - RTE_PKTMBUF_HEADROOM -
+ MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN;
if (frame_size < max_rx_pkt_len) {
MRVL_LOG(WARNING,
"Mbuf size must be increased to %u bytes to hold up "
unsigned int core_id = rte_lcore_id();
if (core_id == LCORE_ID_ANY)
- core_id = rte_get_master_lcore();
+ core_id = rte_get_main_lcore();
if (!q)
return;
if (!priv)
return -EPERM;
+ fc_conf->autoneg = 1;
ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
if (ret) {
MRVL_LOG(ERR, "Failed to read rx pause state");
fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
+ ret = pp2_ppio_get_tx_pause(priv->ppio, &en);
+ if (ret) {
+ MRVL_LOG(ERR, "Failed to read tx pause state");
+ return ret;
+ }
+
+ if (en) {
+ if (fc_conf->mode == RTE_FC_NONE)
+ fc_conf->mode = RTE_FC_TX_PAUSE;
+ else
+ fc_conf->mode = RTE_FC_FULL;
+ }
+
return 0;
}
mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
struct mrvl_priv *priv = dev->data->dev_private;
+ struct pp2_ppio_tx_pause_params mrvl_pause_params;
+ int ret;
+ int rx_en, tx_en;
if (!priv)
return -EPERM;
if (fc_conf->high_water ||
fc_conf->low_water ||
fc_conf->pause_time ||
- fc_conf->mac_ctrl_frame_fwd ||
- fc_conf->autoneg) {
+ fc_conf->mac_ctrl_frame_fwd) {
MRVL_LOG(ERR, "Flowctrl parameter is not supported");
return -EINVAL;
}
- if (fc_conf->mode == RTE_FC_NONE ||
- fc_conf->mode == RTE_FC_RX_PAUSE) {
- int ret, en;
+ if (fc_conf->autoneg == 0) {
+ MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported");
+ return -EINVAL;
+ }
- en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
- ret = pp2_ppio_set_rx_pause(priv->ppio, en);
- if (ret)
- MRVL_LOG(ERR,
- "Failed to change flowctrl on RX side");
+ switch (fc_conf->mode) {
+ case RTE_FC_FULL:
+ rx_en = 1;
+ tx_en = 1;
+ break;
+ case RTE_FC_TX_PAUSE:
+ rx_en = 0;
+ tx_en = 1;
+ break;
+ case RTE_FC_RX_PAUSE:
+ rx_en = 1;
+ tx_en = 0;
+ break;
+ case RTE_FC_NONE:
+ rx_en = 0;
+ tx_en = 0;
+ break;
+ default:
+ MRVL_LOG(ERR, "Incorrect Flow control flag (%d)",
+ fc_conf->mode);
+ return -EINVAL;
+ }
+
+ /* Set RX flow control */
+ ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en);
+ if (ret) {
+ MRVL_LOG(ERR, "Failed to change RX flowctrl");
+ return ret;
+ }
+ /* Set TX flow control */
+ mrvl_pause_params.en = tx_en;
+ /* all inqs participate in xon/xoff decision */
+ mrvl_pause_params.use_tc_pause_inqs = 0;
+ ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params);
+ if (ret) {
+ MRVL_LOG(ERR, "Failed to change TX flowctrl");
return ret;
}
.rxq_info_get = mrvl_rxq_info_get,
.txq_info_get = mrvl_txq_info_get,
.vlan_filter_set = mrvl_vlan_filter_set,
+ .vlan_offload_set = mrvl_vlan_offload_set,
.tx_queue_start = mrvl_tx_queue_start,
.tx_queue_stop = mrvl_tx_queue_stop,
.rx_queue_setup = mrvl_rx_queue_setup,
*l4_offset = *l3_offset + MRVL_ARP_LENGTH;
break;
default:
- MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
break;
}
packet_type |= RTE_PTYPE_L4_UDP;
break;
default:
- MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
break;
}
ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
- if (unlikely(ret < 0)) {
- MRVL_LOG(ERR, "Failed to receive packets");
+ if (unlikely(ret < 0))
return 0;
- }
+
mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
for (i = 0; i < nb_pkts; i++) {
if (unlikely(num <= q->priv->bpool_min_size ||
(!rx_done && num < q->priv->bpool_init_size))) {
- ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
- if (ret)
- MRVL_LOG(ERR, "Failed to fill bpool");
+ mrvl_fill_bpool(q, MRVL_BURST_SIZE);
} else if (unlikely(num > q->priv->bpool_max_size)) {
int i;
int pkt_to_remove = num - q->priv->bpool_init_size;
struct rte_mbuf *mbuf;
struct pp2_buff_inf buff;
- MRVL_LOG(DEBUG,
- "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
- bpool->pp2_id, q->priv->ppio->port_id,
- bpool->id, pkt_to_remove, num,
- q->priv->bpool_init_size);
-
for (i = 0; i < pkt_to_remove; i++) {
ret = pp2_bpool_get_buff(hif, bpool, &buff);
if (ret)
*
* @param ol_flags
* Offload flags.
- * @param packet_type
- * Packet type bitfield.
* @param l3_type
* Pointer to the pp2_ouq_l3_type structure.
* @param l4_type
* Will be set to 1 in case l3 checksum is computed.
* @param l4_cksum
* Will be set to 1 in case l4 checksum is computed.
- *
- * @return
- * 0 on success, negative error value otherwise.
*/
-static inline int
-mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
+static inline void
+mrvl_prepare_proto_info(uint64_t ol_flags,
enum pp2_outq_l3_type *l3_type,
enum pp2_outq_l4_type *l4_type,
int *gen_l3_cksum,
* Based on ol_flags prepare information
* for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
* for offloading.
+ * in most of the checksum cases ipv4 must be set, so this is the
+ * default value
*/
- if (ol_flags & PKT_TX_IPV4) {
- *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
- *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
- } else if (ol_flags & PKT_TX_IPV6) {
+ *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
+ *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
+
+ if (ol_flags & PKT_TX_IPV6) {
*l3_type = PP2_OUTQ_L3_TYPE_IPV6;
/* no checksum for ipv6 header */
*gen_l3_cksum = 0;
- } else {
- /* if something different then stop processing */
- return -1;
}
- ol_flags &= PKT_TX_L4_MASK;
- if ((packet_type & RTE_PTYPE_L4_TCP) &&
- ol_flags == PKT_TX_TCP_CKSUM) {
+ if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) {
*l4_type = PP2_OUTQ_L4_TYPE_TCP;
*gen_l4_cksum = 1;
- } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
- ol_flags == PKT_TX_UDP_CKSUM) {
+ } else if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM) {
*l4_type = PP2_OUTQ_L4_TYPE_UDP;
*gen_l4_cksum = 1;
} else {
/* no checksum for other type */
*gen_l4_cksum = 0;
}
-
- return 0;
}
/**
if (unlikely(!entry->bpool)) {
struct rte_mbuf *mbuf;
- mbuf = (struct rte_mbuf *)
- (cookie_addr_high | entry->buff.cookie);
+ mbuf = (struct rte_mbuf *)entry->buff.cookie;
rte_pktmbuf_free(mbuf);
skip_bufs = 1;
goto skip;
struct pp2_hif *hif;
struct pp2_ppio_desc descs[nb_pkts];
unsigned int core_id = rte_lcore_id();
- int i, ret, bytes_sent = 0;
+ int i, bytes_sent = 0;
uint16_t num, sq_free_size;
uint64_t addr;
sq, q->queue_id, 0);
sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
- if (unlikely(nb_pkts > sq_free_size)) {
- MRVL_LOG(DEBUG,
- "No room in shadow queue for %d packets! %d packets will be sent.",
- nb_pkts, sq_free_size);
+ if (unlikely(nb_pkts > sq_free_size))
nb_pkts = sq_free_size;
- }
for (i = 0; i < nb_pkts; i++) {
struct rte_mbuf *mbuf = tx_pkts[i];
* in case unsupported ol_flags were passed
* do not update descriptor offload information
*/
- ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
- &l3_type, &l4_type, &gen_l3_cksum,
- &gen_l4_cksum);
- if (unlikely(ret))
+ if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
continue;
+ mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
+ &gen_l3_cksum, &gen_l4_cksum);
pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
mbuf->l2_len,
for (i = nb_pkts; i < num; i++) {
sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
MRVL_PP2_TX_SHADOWQ_MASK;
- addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
+ addr = sq->ent[sq->head].buff.cookie;
bytes_sent -=
rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
}
struct pp2_ppio_sg_pkts pkts;
uint8_t frags[nb_pkts];
unsigned int core_id = rte_lcore_id();
- int i, j, ret, bytes_sent = 0;
+ int i, j, bytes_sent = 0;
int tail, tail_first;
uint16_t num, sq_free_size;
uint16_t nb_segs, total_descs = 0;
*/
if (unlikely(total_descs > sq_free_size)) {
total_descs -= nb_segs;
- RTE_LOG(DEBUG, PMD,
- "No room in shadow queue for %d packets! "
- "%d packets will be sent.\n",
- nb_pkts, i);
break;
}
/* In case unsupported ol_flags were passed
* do not update descriptor offload information
*/
- ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
- &l3_type, &l4_type, &gen_l3_cksum,
- &gen_l4_cksum);
- if (unlikely(ret))
+ if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS))
continue;
+ mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type,
+ &gen_l3_cksum, &gen_l4_cksum);
pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type,
l4_type, mbuf->l2_len,
return nb_pkts;
}
-/**
- * Initialize packet processor.
- *
- * @return
- * 0 on success, negative error value otherwise.
- */
-static int
-mrvl_init_pp2(void)
-{
- struct pp2_init_params init_params;
-
- memset(&init_params, 0, sizeof(init_params));
- init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
- init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
- init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
-
- return pp2_init(&init_params);
-}
-
-/**
- * Deinitialize packet processor.
- *
- * @return
- * 0 on success, negative error value otherwise.
- */
-static void
-mrvl_deinit_pp2(void)
-{
- pp2_deinit();
-}
-
/**
* Create private device structure.
*
eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
mrvl_set_tx_function(eth_dev);
eth_dev->dev_ops = &mrvl_ops;
+ eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
+
+ eth_dev->data->dev_link.link_status = ETH_LINK_UP;
rte_eth_dev_probing_finish(eth_dev);
return 0;
return 0;
}
-/**
- * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
- */
-static void
-mrvl_deinit_hifs(void)
-{
- int i;
-
- for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
- if (hifs[i])
- pp2_hif_deinit(hifs[i]);
- }
- used_hifs = MRVL_MUSDK_HIFS_RESERVED;
- memset(hifs, 0, sizeof(hifs));
-}
-
/**
* DPDK callback to register the virtual device.
*
* The below system initialization should be done only once,
* on the first provided configuration file
*/
- if (!mrvl_qos_cfg) {
+ if (!mrvl_cfg) {
cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
MRVL_LOG(INFO, "Parsing config file!");
if (cfgnum > 1) {
goto out_free_kvlist;
} else if (cfgnum == 1) {
rte_kvargs_process(kvlist, MRVL_CFG_ARG,
- mrvl_get_qoscfg, &mrvl_qos_cfg);
+ mrvl_get_cfg, &mrvl_cfg);
}
}
git.droids-corp.org / dpdk.git / blobdiff