net/tap: add in meson build

[dpdk.git] / drivers / net / mvpp2 / mrvl_ethdev.c

diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c
index d5eb1fe..fa4af49 100644 (file)
--- a/drivers/net/mvpp2/mrvl_ethdev.c
+++ b/drivers/net/mvpp2/mrvl_ethdev.c
@@ -29,6 +29,7 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 
+#include <rte_mvep_common.h>
 #include "mrvl_ethdev.h"
 #include "mrvl_qos.h"
 
@@ -63,13 +64,9 @@
 #define MRVL_COOKIE_HIGH_ADDR_SHIFT    (sizeof(pp2_cookie_t) * 8)
 #define MRVL_COOKIE_HIGH_ADDR_MASK     (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
 
-/* Memory size (in bytes) for MUSDK dma buffers */
-#define MRVL_MUSDK_DMA_MEMSIZE 41943040
-
 /** Port Rx offload capabilities */
 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
                          DEV_RX_OFFLOAD_JUMBO_FRAME | \
-                         DEV_RX_OFFLOAD_CRC_STRIP | \
                          DEV_RX_OFFLOAD_CHECKSUM)
 
 /** Port Tx offloads capabilities */
@@ -86,13 +83,12 @@ static const char * const valid_args[] = {
 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 static struct pp2_hif *hifs[RTE_MAX_LCORE];
 static int used_bpools[PP2_NUM_PKT_PROC] = {
-       MRVL_MUSDK_BPOOLS_RESERVED,
-       MRVL_MUSDK_BPOOLS_RESERVED
+       [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
 };
 
-struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
-int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
-uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
+static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
+static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
+static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 
 int mrvl_logtype;
 
@@ -314,12 +310,6 @@ mrvl_dev_configure(struct rte_eth_dev *dev)
                return -EINVAL;
        }
 
-       if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
-               MRVL_LOG(INFO,
-                       "L2 CRC stripping is always enabled in hw");
-               dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
-       }
-
        if (dev->data->dev_conf.rxmode.split_hdr_size) {
                MRVL_LOG(INFO, "Split headers not supported");
                return -EINVAL;
@@ -1335,7 +1325,6 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
 
        /* By default packets are dropped if no descriptors are available */
        info->default_rxconf.rx_drop_en = 1;
-       info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
 
        info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
 }
@@ -1354,6 +1343,8 @@ mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
 {
        static const uint32_t ptypes[] = {
                RTE_PTYPE_L2_ETHER,
+               RTE_PTYPE_L2_ETHER_VLAN,
+               RTE_PTYPE_L2_ETHER_QINQ,
                RTE_PTYPE_L3_IPV4,
                RTE_PTYPE_L3_IPV4_EXT,
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
@@ -1923,13 +1914,27 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
 {
        enum pp2_inq_l3_type l3_type;
        enum pp2_inq_l4_type l4_type;
+       enum pp2_inq_vlan_tag vlan_tag;
        uint64_t packet_type;
 
        pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
        pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
+       pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
 
        packet_type = RTE_PTYPE_L2_ETHER;
 
+       switch (vlan_tag) {
+       case PP2_INQ_VLAN_TAG_SINGLE:
+               packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
+               break;
+       case PP2_INQ_VLAN_TAG_DOUBLE:
+       case PP2_INQ_VLAN_TAG_TRIPLE:
+               packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
+               break;
+       default:
+               break;
+       }
+
        switch (l3_type) {
        case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
                packet_type |= RTE_PTYPE_L3_IPV4;
@@ -2652,23 +2657,16 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
                goto init_devices;
 
        MRVL_LOG(INFO, "Perform MUSDK initializations");
-       /*
-        * ret == -EEXIST is correct, it means DMA
-        * has been already initialized (by another PMD).
-        */
-       ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
-       if (ret < 0) {
-               if (ret != -EEXIST)
-                       goto out_free_kvlist;
-               else
-                       MRVL_LOG(INFO,
-                               "DMA memory has been already initialized by a different driver.");
-       }
+
+       ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
+       if (ret)
+               goto out_free_kvlist;
 
        ret = mrvl_init_pp2();
        if (ret) {
                MRVL_LOG(ERR, "Failed to init PP!");
-               goto out_deinit_dma;
+               rte_mvep_deinit(MVEP_MOD_T_PP2);
+               goto out_free_kvlist;
        }
 
        memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
@@ -2693,11 +2691,10 @@ out_cleanup:
        for (; i > 0; i--)
                mrvl_eth_dev_destroy(ifnames.names[i]);
 
-       if (mrvl_dev_num == 0)
+       if (mrvl_dev_num == 0) {
                mrvl_deinit_pp2();
-out_deinit_dma:
-       if (mrvl_dev_num == 0)
-               mv_sys_dma_mem_destroy();
+               rte_mvep_deinit(MVEP_MOD_T_PP2);
+       }
 out_free_kvlist:
        rte_kvargs_free(kvlist);
 
@@ -2737,7 +2734,7 @@ rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
                MRVL_LOG(INFO, "Perform MUSDK deinit");
                mrvl_deinit_hifs();
                mrvl_deinit_pp2();
-               mv_sys_dma_mem_destroy();
+               rte_mvep_deinit(MVEP_MOD_T_PP2);
        }
 
        return 0;
@@ -2751,9 +2748,7 @@ static struct rte_vdev_driver pmd_mrvl_drv = {
 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
 
-RTE_INIT(mrvl_init_log);
-static void
-mrvl_init_log(void)
+RTE_INIT(mrvl_init_log)
 {
        mrvl_logtype = rte_log_register("pmd.net.mvpp2");
        if (mrvl_logtype >= 0)