ethdev: make default behavior CRC strip on Rx

[dpdk.git] / drivers / net / mvpp2 / mrvl_ethdev.c

diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c
index fdf416b..fa4af49 100644 (file)
--- a/drivers/net/mvpp2/mrvl_ethdev.c
+++ b/drivers/net/mvpp2/mrvl_ethdev.c
@@ -67,7 +67,6 @@
 /** Port Rx offload capabilities */
 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
                          DEV_RX_OFFLOAD_JUMBO_FRAME | \
-                         DEV_RX_OFFLOAD_CRC_STRIP | \
                          DEV_RX_OFFLOAD_CHECKSUM)
 
 /** Port Tx offloads capabilities */
@@ -87,9 +86,9 @@ static int used_bpools[PP2_NUM_PKT_PROC] = {
        [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
 };
 
-struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
-int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
-uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
+static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
+static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
+static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 
 int mrvl_logtype;
 
@@ -311,14 +310,6 @@ mrvl_dev_configure(struct rte_eth_dev *dev)
                return -EINVAL;
        }
 
-       /* KEEP_CRC offload flag is not supported by PMD
-        * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
-        */
-       if (rte_eth_dev_must_keep_crc(dev->data->dev_conf.rxmode.offloads)) {
-               MRVL_LOG(INFO, "L2 CRC stripping is always enabled in hw");
-               dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
-       }
-
        if (dev->data->dev_conf.rxmode.split_hdr_size) {
                MRVL_LOG(INFO, "Split headers not supported");
                return -EINVAL;
@@ -1334,7 +1325,6 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
 
        /* By default packets are dropped if no descriptors are available */
        info->default_rxconf.rx_drop_en = 1;
-       info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
 
        info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
 }
@@ -1353,6 +1343,8 @@ mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
 {
        static const uint32_t ptypes[] = {
                RTE_PTYPE_L2_ETHER,
+               RTE_PTYPE_L2_ETHER_VLAN,
+               RTE_PTYPE_L2_ETHER_QINQ,
                RTE_PTYPE_L3_IPV4,
                RTE_PTYPE_L3_IPV4_EXT,
                RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
@@ -1922,13 +1914,27 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
 {
        enum pp2_inq_l3_type l3_type;
        enum pp2_inq_l4_type l4_type;
+       enum pp2_inq_vlan_tag vlan_tag;
        uint64_t packet_type;
 
        pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
        pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
+       pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
 
        packet_type = RTE_PTYPE_L2_ETHER;
 
+       switch (vlan_tag) {
+       case PP2_INQ_VLAN_TAG_SINGLE:
+               packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
+               break;
+       case PP2_INQ_VLAN_TAG_DOUBLE:
+       case PP2_INQ_VLAN_TAG_TRIPLE:
+               packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
+               break;
+       default:
+               break;
+       }
+
        switch (l3_type) {
        case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
                packet_type |= RTE_PTYPE_L3_IPV4;