#define NGBE_EM_RAR_ENTRIES 32
#define NGBE_EM_MC_TBL_SIZE 32
#define NGBE_EM_VFT_TBL_SIZE 128
+#define NGBE_EM_RX_PB_SIZE 42 /*KB*/
s32 ngbe_init_hw(struct ngbe_hw *hw);
s32 ngbe_start_hw(struct ngbe_hw *hw);
ngbe_mc_addr_itr func, bool clear);
s32 ngbe_disable_sec_rx_path(struct ngbe_hw *hw);
s32 ngbe_enable_sec_rx_path(struct ngbe_hw *hw);
+void ngbe_set_pba(struct ngbe_hw *hw);
s32 ngbe_setup_fc_em(struct ngbe_hw *hw);
s32 ngbe_fc_enable(struct ngbe_hw *hw);
s32 ngbe_validate_mac_addr(u8 *mac_addr);
s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask);
void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask);
+s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable);
s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);
s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);